Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Ming Ke

Tsai-Sheng Gau

Kai-Hsiung Chen

Yang-Hung Chang

Te-Chih Huang

Chun-Ming Hu

Li-Jui Chen

Shinn-Sheng Yu

Yen-Liang Chen

Fu-Jye Liang

Jacky Huang

Guo-Tsai Huang

Che-Yuan Sun

Jia-Rui Hu

Tzung-Chi Fu

Heng-Jen Lee

Hung-Chih Hsieh

Wen-Zhan Zhou

Kai Wu

Chang-Tsun Hsieh

Weimin Hu

Chin-Hsiang Lin

Po-Chung Cheng

Chun-Kuang Chen

Hua-Tai Lin

Jaw-Jung Shin

Jen-Chieh Shih

Ho-Yung David Hwang

Bang-Ching Ho

Chen-Ming Wang

Anthony Yen

Heng-Hsin Liu

Shy-Jay Lin

Burn Jeng Lin

Hung-Chang Hsieh

Joung-Wei Liou

Wen-Chuan Wang

Chyi Shyuan Chern

Szu-An Wu

Yun-Hung Shen

Hsin-Hsien Wu

Yao-Ching Ku

Burn-Jeng Lin

Pei-Hung Chen

Jyuh-Fuh Lin

Chien-Hsun Lin

Wei-Yu Su

Kuo-Chen Huang

Jiann Yuan Huang

Jieh-Ting Chang

Hung-Bin Lin

Ching-Pin Kao

Li-Chao Yin

Kai-Hsiung Cheng

Shu-Chuan Chuang

Li-Jiu Chen

Yu-Hsi Wang

Anderson Chang

Shing-Sheng Yu

Tsai-Sheng Giau

Ming-Hua Lo

In a method, a structure including two or more materials having different coefficients of thermal expansion is prepared, and the structure is subjected to a cryogenic treatment. In one or more of the foregoing and following embodiments, the structure includes a semiconductor wafer and one or more layers are formed on the semiconductor wafer.

Method of manufacturing semiconductor devices

A method for performing DBO measurements utilizing apertures having a single pole includes using a first aperture plate to measure X-axis diffraction of a composite grating. In some embodiments, the first aperture plate has a first pair of radiation-transmitting regions disposed along a first diametrical axis and on opposite sides of an optical axis that is aligned with a center of the first aperture plate. Thereafter, in some embodiments, a second aperture plate, which is complementary to the first aperture plate, is used to measure Y-axis diffraction of the composite grating. By way of example, the second aperture plate has a second pair of radiation-transmitting regions disposed along a second diametrical axis and on opposite sides of the optical axis. In some cases, the second diametrical axis is substantially perpendicular to the first diametrical axis.

Aperture design and methods thereof

The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.

Noise reduction for overlay control

A spectroscopic overlay metrology system and corresponding spectroscopic overlay metrology methods are disclosed herein for improving overly measurement accuracy, optimizing overlay recipes, and/or minimizing (or eliminating) asymmetry-induced overly error from overlay measurements. An exemplary method includes generating a diffraction spectrum by an overlay target from incident radiation having more than one wavelength. The diffraction spectrum includes a plurality of positive ordered diffracted beams and a plurality of negative ordered diffracted beams that are separated by wavelength, such that the diffraction spectrum includes more than one wavelength of a positive order and a negative order. The method further includes collecting intensity information associated with the diffraction spectrum generated by the overlay target from the incident radiation, and generating overlay information from the collected intensity information, where the overlay information includes contributions from asymmetry-induced overlay error. In some implementations, the method includes optimizing an overlay recipe based on the generated overlay information.

Spectroscopic overlay metrology

Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Forecasting wafer defects using frequency domain analysis

A method includes selecting a group of wafers, each of the wafers having a resist pattern; selecting a group of fields for each of the wafers; selecting one or more points on each of the fields; measuring overlay errors on the resist pattern at locations associated with the one or more points selected on the respective wafers; and generating a combined overlay correction map based on measurements of the overlay errors on the wafers. At least one of the selecting of the group of wafers, the selecting of the group of fields, and the selecting of the one or more points is based on a computer-generated model.

Method and system for overlay control

The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions.

Two-dimensional marks

A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.

Method of extracting defects

Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated. Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Growing community of inventors

Hsinchu, Taiwan

Chih-Ming Ke