Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Asustek Computer Inc.

Inventec Corp.

Inventec (pudong) Technology Corporation

Neodio Technologies Corporation

Chih-Lung Lin

Cheng-Yuan Tsai

Shwang-Ming Jeng

Keng-Chu Lin

You-Hua Chou

Chyi-Shyuan Chern

Cheng-Chen Calvin Hsueh

Soon Kang Huang

Kuan-Chen Wang

Fang-Wen Tsai

Chen-Hua Douglas Yu

Tien-I Bao

Chien-Hung Zordius Chen

Zhen-Cheng Wu

Wen-Cheng Chien

Hsiao-Te Chang

Fang Wen Tsai

Yi-Ching Chen

I-i Chen

Tsung-Lin Wu

Te-Son Kuo

Shuenn-Tsong Young

Han-Chang Wu

Chao-Ming Liu

Chin-Hung Lin

Wei-Chung Hung

Huai-Hao Syu

Chen-Chin Kuo

Tzu-Ping Lin

Chia-Po Chou

Jia Lung Wang

Han-Wei Tang

Shih Chieh Su

Pei-Yu Chen

Ping-Fu Hsieh

Y C Chang

An automatically brightness adjusting electronic device and a brightness adjusting method are provided. The method comprises: sensing an environmental light intensity; generating a brightness adjustment signal according to the environmental light intensity via a second control unit; and adjusting a display brightness of a display unit according to the brightness adjustment signal via a first control unit or the second control unit.

Automatically brightness adjusting electronic device and brightness adjusting method thereof

A control method of a control system includes storing output data to a memory according to a buffer pointer when a clock signal converts to a second level from a first level; storing input data to the memory according to the buffer pointer when the clock signal converts to the first level from the second level; and updating the buffer point.

Control method for storing data according to buffer pointer at clock signal conversions

A computer includes an application system, a storage device and a basic input output system (BIOS). The application system can be respectively coupled to the storage device and the BIOS, set at least a multimedia file as a preset playing file according to an input instruction and store the preset playing file into the storage device. The application system can further generate a log file according to the input instruction and the storage position of the preset playing file, wherein the log file is sent to the BIOS. The BIOS has a file access module, so that the BIOS can acquire the preset playing file from the storage device according to the log file for playing during booting the computer.

Computer, booting software product and computer booting method

A method of forming an isolation structure includes the steps of: (a) forming an opening within a substrate; (b) forming a substantially conformal layer comprising tetraethoxysilane (TEOS) layer along the opening; and (c) forming a dielectric layer over the TEOS layer, the dielectric layer substantially filling the opening.

Isolation structures and methods of fabricating isolation structures

A wet cleaning solution, comprising 0.01-3 wt % of an amphoteric imidazolium surfactant capable of forming a complex with metal ions, a pH adjuster, and balanced deionized water. The wet cleaning solution is substantially free of corrosion inhibitor other than the imidazolium amphoteric surfactant.

Wet cleaning solution

An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.

Extreme low-K dielectric film scheme for advanced interconnects

A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.

Retainer ring

Extreme low-k dielectric film scheme for advanced interconnect

A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.

Method for forming dielectric film to improve adhesion of low-k film

A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)&#x2dc;(d) are repeated until a high density dielectric film is formed on the substrate.

Method for forming a high density dielectric film by chemical vapor deposition

A method for enhancing stability of a fluorinated silicon glass layer is disclosed. A fluorinated silicon glass layer provided on a substrate is subjected to a phosphorous-containing and hydrogen-containing gas such as phosphine (PH), for example. The gas forms reactive hydrogen species which removes fluorine radicals and reactive phosphorous species which forms a moisture-gettering and ion-gettering phosphorious oxide film the layer.

Method for enhancing FSG film stability

A plug-and-play(PnP) interconnection architecture and method with an in-device storage module in a peripheral device are proposed for interconnecting a peripheral device with a host computer unit. The proposed architecture is characterized by integration of an in-device storage unit with internal functional modules of the peripheral device for storing device specific data and software such as the dedicated device driver of the peripheral device. An enhanced plug-and-play (ePnP) layered structure is proposed based on the in-device storage architecture. The ePnP provides a mechanism to PnP peripheral devices' functions customization. An application of the ePnP is the mechanism to bring up the device driver automatically when the peripheral device is connected to the host computer unit. This auto-installation mechanism provides a truly plug-and-play capability to the user.

Plug-and-play interconnection architecture and method with in-device storage module in peripheral device

Within a chemical mechanical polish (CMP) method there is first provided a first control substrate, a first series of product substrates and a second control substrate. There is then sequentially chemical mechanical polish (CMP) planarized, while employing a chemical mechanical polish (CMP) planarizing method, the first control substrate to provide a planarized first control substrate, the first series of product substrates to provide a planarized first series of product substrates and the second control substrate to provide a planarized second control substrate. There is then determined, for the planarized first control substrate and the planarized second control substrate, a corresponding first value of a parameter within the chemical mechanical polish (CMP) planarizing method and a corresponding second value of the parameter within the chemical mechanical polish (CMP) planarizing method. There may then be interpolated or extrapolated from the first value of the parameter and the second value of the parameter to provide an interpolated value of the parameter for a planarized first product substrate within the planarized first series of product substrates or an extrapolated value of the parameter which may be employed for planarizing with enhanced uniformity a second product substrate within a second series of product substrates.

In-line chemical mechanical polish (CMP) planarizing method employing interpolation and extrapolation

A method for on-chip polishing pad conditioning in a chemical mechanical polishing process is disclosed. In the method, a plurality of dummy patterns in a designated area on a wafer surface are planted during the same photolithographic method for forming the IC dies. The designated area may be the edge portion, i.e., the blanket area along the edges of a wafer, or the scribe lines formed on the wafer. The dummy patterns should be formed to a step height of at least 2,000 &angst;, and preferably to at least 4,000 &angst;. The present invention plurality of dummy patterns is used during a polishing process for the top surface of a semiconductor wafer by a polishing pad. The plurality of dummy patterns simultaneously conditions the pad in a localized manner to improve the removal rate of the pad. The shape of the dummy patterns can be formed in any desirable shape, including those that have a cross-section of a square or a rectangle with a width of at least 100 &angst;.

On-chip pad conditioning for chemical mechanical polishing

Growing community of inventors

Taipei, Taiwan

Chih-Lung Lin