Realtek Semiconductor Inc.

Wistron Neweb Corporation

Industrial Technology Research Institute

Other

Chipbond Technology Corporation

Realtek Semiconductor Corporate

Chih-Lung Chen

Shih-Hsiung Huang

Jie-Fan Lai

Yu-Chang Chen

Chien-Ming Wu

Ka-Un Chan

Liang-Huan Lei

Hsuan-Yi Su

Chih-Chan Tu

Kuan-Hsueh Tseng

Jing-Wen Tang

Tai-Cheng Lee

Sheng-Hsiung Lin

Wei-Li Cheng

Hung-Yue Chang

Wei-Chen Lin

Wen-Hsien Sun

Chen-Hsing Fang

Yen-Po Lai

Liang-Wei Huang

Po-Chih Wang

Shih-Hong Chen

Chia-Jun Chang

Chung-Hsien Wu

Hong-Dun Lin

Chien-Hong Lin

Jiunn-Ming Huang

Chia-Jung Tu

Cheng-Pang Chan

John Chungteh Pan

Chi-Lung Wang

Sheng-Yen Shih

Francis Chung Hwa Pan

Chih-Kai Liu

Ying-Cheng Wu

Kuo-Sheng Chung

Tzu-Hsien Han

Yen-Hsien Lee

Chi-Ying Lee

Chun-Chi Lee

Yung-Pin Huang

Tzu-Hao Hung

Pei-Yi Yeh

Shu-Lin Chang

Bi-Ching Huang

Cheng-Hui Wu

Li-Jun Chen

Pei-Fen Zhen

Pei-Ying Chao

Ruey-Ling Liu

Wen-Hsiang Liao

Chung-Hsiang Wei

Yung-Chi Liu

Kuo-Hsing Lee

Han-Chang Pan

Tzung-Ling Tsai

Zong-Yau Yin

Sie-siou Jhang-jian

Yao-Ming Lu

Yan-Hui Wu

Yong-Syuan Chen

A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.

Continuous-time delta-sigma modulator

A low-dropout regulator system includes a low-dropout regulator. A comparator circuit generates a comparison voltage according to a reference voltage and a feedback voltage. An amplifier circuit generates an amplifying voltage according to the comparison voltage. A transistor receives an input voltage and is controlled by the amplifying voltage to generate an output voltage at an output terminal. A first resistor circuit is coupled between a first node and a ground terminal. A second resistor circuit is coupled between the output terminal and the first node. At a start-up timing point of the low-dropout regulator, a resistance value of the second resistor circuit is a first resistance value. After the input voltage reaches a maximum voltage, the resistance value of the second resistor circuit is a second resistance value. The second resistance value is larger than the first resistance value.

Low-dropout regulator system and control method thereof

A signal adjusting circuit and a receiving end circuit using the same are provided. The signal adjusting circuit is adapted to a peak detector, and includes a first amplifier and a first feedback circuit. The first amplifier receives a first input signal, and amplifies the first input signal to output a first output signal. The first feedback circuit is connected between a first input terminal and a first output terminal of the first amplifier, and is configured to determine a first gain of the first output signal. The peak detector is connected to a first output node of the first feedback circuit, so as to receive a first detection signal and detect a peak value of the first detection signal. The peak detector has a predetermined power input range, and the first feedback circuit keeps the first detection signal within the predetermined power input range.

Signal adjusting circuit and receiving end circuit using the same

A temperature sensing circuit that includes a bandgap voltage generation circuit, a current mirror branch, a variable resistor, a comparator circuit, a control circuit and a temperature determining circuit. The bandgap voltage generation circuit generates a bandgap voltage. The current mirror branch generates a mirrored current mirrored from the bandgap voltage generation circuit. The variable resistor is electrically coupled to the current mirror branch to receive the mirrored current to generate a variable voltage. The comparator circuit compares the bandgap voltage and the variable voltage to generate a comparison result. The control circuit generates a control signal according to the comparison result to adjust the resistance of the variable resistor and outputs a signal value when the signal value forces the variable voltage to be equal to the bandgap voltage. The temperature determining circuit generates a temperature value according to the signal value.

Temperature sensing circuit

An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

Amplifier circuit

An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.

Analog circuit and comparator sharing method of analog circuit

A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method.

Calibration device and calibration method

An antenna device is provided. The antenna device includes an antenna layer, a first transparent layer, and a second transparent layer. The antenna layer is a metal mesh structure having a plurality of thru-holes, and the antenna layer includes at least one soldering region and an embedded region. The first transparent layer and the second transparent layer are respectively connected to two opposite sides of the antenna layer. The first transparent layer and the second transparent layer are connected to each other, so that the embedded region of the antenna layer is embedded in-between the first transparent layer and the second transparent layer. The second transparent layer has a hollow region corresponding in position to the at least one soldering region, so that the at least one soldering region is exposed from the hollow region.

Antenna device

A filter includes multiple filter circuits. The filter circuits are coupled in series between an input terminal and an output terminal, to generate an output signal according to an input signal. One of the filter circuits operates as an active filter circuit or a passive filter circuit according to amplitude of the input signal.

Filter, filtering method, and filter system

A composite structure and dispersion employing the same are provided. The composite structure includes 1 part by weight of silver nanowires, and 1.2 to 3 parts by weight of nanofibers, wherein the diameter of the silver nanowires and the diameter of the nanofibers have a ratio of 1:1 to 1:10.

Composite structure and dispersion

A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.

Filter and filtering method

An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

Analog to digital converter device and noise shaping digital slope analog to digital converter circuitry

Disclosed is a differential amplifier including an input circuit, a detecting and controlling circuit, and an output circuit. The input circuit outputs input current to two output nodes according to the voltage of a differential input signal and the voltage of a bias node. The detecting and controlling circuit outputs compensative current to the two output nodes according to control bias voltage and the voltage of the bias node, in which the voltage of the bias node and the compensative current relate to the voltage of the differential input signal. The output circuit is coupled to the two output nodes and outputs a differential output signal according to the sum of the input current and the compensative current. Due to the detecting and controlling circuit outputting the compensative current, the differential amplifier prevents itself from entering a deadlock state even though the input current is insufficient or zero.

Differential amplifier

An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

Analog-to-digital converter

Disclosed is a radio-frequency (RF) circuit capable of performing an RF characteristic test in a test mode. The RF circuit includes: a test signal generator generating a test signal; an RF receiver, coupled to the test signal generator, transmitting the test signal and thereby generating a receiver analog signal; a coupling circuit transmitting the receiver analog signal to an RF transmitter in the test mode; the RF transmitter transmitting the receiver analog signal and thereby generating a transmitter analog signal; a test result generator, coupled between the RF transmitter and a test result output terminal, including a signal converter for generating a converted signal according to the transmitter analog signal in the test mode, wherein the output signal at the test result output terminal is the converted signal or originated therefrom and relates to the result of the RF characteristic test.

Radio-frequency circuit

Growing community of inventors

Hsinchu County, Taiwan

Chih-Lung Chen