Eon Silicon Devices, Inc.

Spatial Photonics, Inc.

Micropixel, Inc.

Chih-Liang Chen

James C Yu

Chien-Sheng Su

I-Chuin Peter Chan

Alex Hung-Pin Sun

Chao-Ven Kao

A spatial light modulator having two static random access memory (SRAM) devices, including a display controller configured with a display sequence, the display sequence including a first display slice and a second display slice, the first display slice having a display time less than two times a minimum time period determined by the time of a write event, and the second display slice having a display time of more than two times the minimum time period. The controller controls write events from the two SRAM devices, and the first display slice and second display slice are ordered in the display sequence so that the controller causes the spatial light modulator to output light and causes the two SRAM devices each to perform a write event during the second display slice.

Spatial modulator display system using two memories and display time slices having differing times

A Silicon-Chip-Display (SCD) cell structure operable in a field sequential mode for use in liquid crystal display (LCD) devices and a method for operating the same provided. The SCD cell structure is formed of first through third write-enable transistors, first through third storage capacitors, and first through third display-enable transistors. In one preferred embodiment, each of the write-enable transistors is sequentially turned on so to pre-load video data into the corresponding storage capacitors during one color-field time prior to when each of the corresponding display-enable transistors is sequentially turned on for displaying an associated color-field. As a consequence, there is rendered a higher quality video image by allowing the LC response time and/or the light strobing time to be increased.

Silicon-Chip-Display cell structure

An output noise control circuit with significantly reduced power/ground bounce characteristics when multiple outputs thereof are being simultaneously switched is provided. The output noise control circuit includes a plurality of output buffers each being formed of an output driver stage, a first pre-driver stage, and a second pre-driver stage. Each of the output driver stages includes a pull-up drive transistor and a pull-down drive transistor. Each of the first pre-driver stages includes a first inverter, and each of said second pre-driver stages includes a second inverter. A shared pull-up resistor has its one end coupled to each of the first pre-driver stage inverters and its other end connected to a ground potential node. A shared pull-down resistor has its one end coupled to each of the second pre-driver stage inverters and its other end connected to a power supply potential node. The output noise control circuit is formed with a reduced number of circuit components than the traditional output buffer circuits currently available.

Output noise control scheme for multiple I/O's

The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one conductivity type formed in a second region of the opposite conductivity type, source and drain regions of the opposite conductivity type formed in the first semiconductor region, and a gate. The second region is formed within a substrate of the one conductivity type. The gate includes a control gate and a floating gate, which retains charge and overlies the first semiconductor region. The erase method of the invention includes the steps of: applying a first voltage of one polarity to the source region and the first and second semiconductor regions; and simultaneously applying a second voltage of the opposite polarity to the gate, whereby any charge on the floating gate tunnels through the floating gate dielectric into both the first region and the source region, thereby removing any charge retained by the floating gate.

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Saratoga, CA, United States of America

Chih-Liang Chen