Via Technologies, Inc.

Chih-Kuo Kao

Jiin Lai

Chau-Chad Tsai

Chi-Che Tsai

Peter Chia

Chia-Hsin Chen

Sheng-Chang Peng

Wei-Hsiang Hong

Yao-Chun Su

Chad Tsai

Edward Su

A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the upstream unit and the downstream unit, wherein the endpoint device asserts at least one request to the upstream unit. The request scheduling method includes: transmitting the request to a processing unit while the request is a non-peer-to-peer request, and transmitting the request to a downstream unit while the request is a peer-to-peer request; wherein if the request is a peer-to-peer and posted request and there is a previous asserted request which is peer-to-peer and non-posted request and the previous asserted request has a latency exceeds a predetermined time, transmitting the request earlier than the previous asserted request to the downstream unit.

Method and system for request accessing and scheduling

The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.

Chipset supporting a peripheral component interconnection express (PCI-E) architecture

The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

Method of hot switching data transfer rate on bus

A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.

Bus for supporting plural signal line configurations and switch method thereof

A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

Memory-access management method and system for synchronous dynamic Random-Access memory or the like

A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.

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Taipei, Taiwan

Chih-Kuo Kao