Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Chih-Kuang Kao

Huei-Wen Yang

Ta-Chih Peng

Ming-Hong Kao

Yu-Wen Lin

Yung-Sheng Huang

Chih-Feng Ku

Yu-Ching Chiu

The present disclosure describes a method that includes scanning a circuit layout and identifying layout regions of the circuit layout. The method further includes placing unit cells in a layout region of the layout regions and forming a micro pad structure at a border of a unit cell of the unit cells. The micro pad structure includes interconnect structures that are electrically connected to the unit cell.

Array of unit cells having pad structures

The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Semiconductor structure and method of forming the same

A capacitor structure includes a first electrode, a second electrode, a third electrode, a first dielectric layer and a second dielectric layer. The second electrode is disposed over the first electrode. The third electrode is disposed over the second electrode. The first dielectric layer is disposed between the first electrode and the second electrode. The second dielectric layer is disposed between the second electrode and the third electrode. The third electrode contacts the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.

Semiconductor structure and method for manufacturing capacitor structure

Semiconductor structure and method of forming semiconductor package

A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.

Capacitor structure and semiconductor structure

The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.

Semiconductor package and method of forming the same

Capacitor structure and method for manufacturing the same

A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Barrier layer for copper interconnect

A waveform correction apparatus is disclosed. The waveform correction apparatus includes a signal generator for generating a signal; a maximal value recorder for recording a maximal value of the signal waveform; a minimal value recorder for recording a minimal value of the signal waveform; a difference value generator for generating a difference value of the maximal value and the minimal value; and a comparative controller for comparing the difference value with a reference value. The comparative controller outputs a corrected waveform when the difference value is larger than the reference value, otherwise it outputs the original waveform generated by the waveform generator. The corrected waveform is formed by shifting up or down the original waveform by a constant value.

Growing community of inventors

Hsin-Chu County, Taiwan

Chih-Kuang Kao