United Microelectronics Corp.

Chih-Kai Kang

Sheng-Yuan Hsueh

Yi-Chung Sheng

Kuo-Hsing Lee

Ting-Hsiang Huang

Chien-Liang Wu

Guan-Kai Huang

Wen-Kai Lin

Chi-Horn Pai

Shu-Hung Yu

Hsin-Hsien Chen

Shih-Chieh Hsu

Chia-Chen Sun

Po-Kuang Hsieh

Kuo-Yu Liao

Hsiang-Hung Peng

Yung-Chen Chiu

Hung-Hsu Lin

Shu-Hsuan Chih

Chun-Hsien Lin

Po-Cheng Huang

Po-Jui Liao

Jie-Ning Yang

Yao-Chang Wang

Chi-Sheng Tseng

Kuang-Hung Huang

Shih-Chang Chang

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Magnetoresistive random access memory

A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

Bit cell structure for one-time-programming

A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

High electron mobility transistor (HEMT) and forming method thereof

A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

3D semiconductor structure and method of fabricating the same

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.

A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.

Method of forming fin forced stack inverter

A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

Mark pattern in semiconductor device

A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.

Semiconductor device

A magnetic random access memory (MRAM) includes device strings coupled in parallel, each comprising magnetic tunnel junctions (MTJs) coupled in serial, wherein a quantity of the MTJs of each of the device strings is equal to a quantity of the device strings, and an equivalent resistance (R) of the MTJs is equal to an average of the sum of a high resistance of one of the MTJs and a low resistance of another MTJ.

Growing community of inventors

Tainan, Taiwan

Chih-Kai Kang