United Microelectronics Corp.

Untied Microelectronics Corp.

Chih-Kai Hsu

Ssu-I Fu

Jyh-Shyang Jenq

Yu-Hsiang Hung

Yu-Hsiang Lin

Chin-Hung Chen

Chun-Ya Chiu

Chia-Jung Hsu

Chi-Ting Wu

Wei-Chi Cheng

Chao-Hung Lin

Shih-Hung Tsai

Li-Wei Feng

Chien-Ting Lin

Tsai-Yu Wen

Shi You Liu

Ching-Yu Chang

Yi-Wei Chen

Ching-Wen Hung

Chih-Sen Huang

Yi-Hui Lee

Jia-Rong Wu

Ying-Chiao Wang

Ying-Cheng Liu

Tsung-Mu Yang

Ying-Tsung Chen

Yi-Kuan Wu

Yu-Cheng Tung

En-Chiuan Liou

Chien-Hung Chen

Chun-Hsien Huang

Yu-Tse Kuo

Wen-Fang Lee

An-Chi Liu

Shu-Ru Wang

Chiu-Te Lee

Chung-Fu Chang

Nien-Chung Li

Yen-Liang Wu

Po-Wen Su

Ching-Chung Yang

Shih-Fang Hong

Shin-Hung Li

Chun-Tsen Lu

Chang-Po Hsiung

Hon-Huei Liu

Chia-Hsun Tseng

Shan-Shi Huang

Chih-Wei Wu

Guang-Yu Lo

Mei-Chen Chen

Chun Yu Chen

A static random access memory (SRAM) includes a substrate having a first active region and a second active region adjacent to the first active region. A first gate structure is disposed on the substrate and across the first active region and the second active region. A second gate structure is adjacent to a first side of the first gate structure. A first lower contact structure is disposed on the first active region and adjacent to a second side of the first gate structure. A first upper contact structure is disposed on and in direct contact with the first lower contact structure. A top surface of the first lower contact structure and a sidewall of the first upper contact structure comprise a step profile therebetween.

Static random access memory

A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Method for integrating high-voltage (HV) device, medium-voltage (MV) device, and low-voltage (LV) device

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

High voltage transistor structure

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

Manufacturing method of semiconductor device

Growing community of inventors

Tainan, Taiwan

Chih-Kai Hsu