Phison Electronics Corporation

Industrial Technology Research Institute

Phisontech Electronics (malaysia) Sdn Bhd.

Chih-Jen Hsu

Wee-Kuan Gan

Yi-Hsiang Huang

Ming-Jen Liang

Hsiang-Hsiung Yu

Yun-Chieh Chen

Yue-Min Jiang

Szu-Han Tzao

Chung-Lin Wu

Ho-Hsin Lee

Ta-Chuan Wei

Duan-Yu Chen

Nyuk-How Thian

Tsai-Ya Lai

A system for object recognition includes an image/spectrum sensing device, to fetch an object image from a real object and sense spectra at sensing regions of the real object. A fetching module obtains a real-object image feature pattern for each ROI of the object image. An analyzing module for object image feature searches for a first candidate object from data bank and analyzes a correlation between the real object and candidate object. A fetching module for object spectrum feature obtains a real-object spectrum pattern for each ROI of the object image. An analyzing module for object spectrum feature is to search for a second candidate object from data bank and to further analyze a match level between the real-object and the second candidate object. A fusion module further analyzes information of image feature and spectrum feature find whether or not having a matched object as an identify object.

System and method for object recognition

A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.

Memory storage device, memory control circuit unit and power supply method

A clock adjustment circuit and a digital to analog converting device are provided. The clock adjustment circuit includes a selection circuit and a frequency decreasing circuit. The selection circuit is configured to generate a first selection signal in response to a frequency of an output clock signal. The frequency decreasing circuit is coupled to the selection circuit, and configured to generate the output clock signal by reducing a frequency of an input clock signal by a first ratio in response to a first level of the first selection signal, and configured to generate the output clock signal by reducing the frequency of the input clock signal by a second ratio in response to a second level of the first selection signal, wherein the first ratio is different from the second ratio. Accordingly, complexity of a circuit is reduced.

Clock adjustment circuit and digital to analog converting device

A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.

Flash memory storage device, controller thereof, and data programming method thereof

Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.

Data accessing method, controller and storage system using the same

A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.

Bad block identifying method for flash memory, storage system, and controller thereof

A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0xFF data in the data area and writes all 0xFF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0xFF data and the all 0xFF error-correcting codes into all 0x00 data and all 0x00 error-correcting codes, respectively.

Controller and storage device having the same

The present invention describes a modulator including a differential amplifier connected to a reference voltage and a first transistor, and the first transistor is connected to a feedback device, and a second transistor is set between the first transistor and the differential amplifier and connected to a voltage detector and a diode, and the diode is connected to a power supply, and the voltage detector keeps on detecting an output voltage (VOUT) between the feedback device and the first transistor. If the output voltage (VOUT) value is lower than a predetermined voltage value of the power supply, the voltage detector will issue a signal to drive the second transistor and limit a gate-source voltage (VGS) of the first transistor within a voltage difference of the diode, so as to reduce the impetus of the first transistor and avoid the phenomenon of a sudden climb with an excessively large output voltage (VOUT).

Modulator

A detect/modulate circuit comprises a plurality of modulate resistors connected to a main resistor of a bandgap in series, and each module resistor is connected to a transistor switch in parallel, and each transistor switch is connected to a logic controller, and the logic controller is connected in sequence to a plurality of detect circuits and fuses corresponding to the quantity of the transistor switches. When the detect circuit receives a low-to-high power-on reset signal to detect whether or not the fuse is fused, the detect circuit will issue a voltage level signalfor the fuse being not fused or a voltage level signalfor the fuse being fused to the logic controller. The logic controller converts the received voltage level signal according to a logic conversion table to control the electric connection of the corresponding transistor switch, so as to fine turn the main resistance of the bandgap.

Detect/modulate circuit

A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0xFF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0xFF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0xFF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0xFF.

Growing community of inventors

Hsinchu County, Taiwan

Chih-Jen Hsu