Nan Ya Technology Corporation

Delta Electronics, Inc.

Chih-Jen Chen

Ting-Shuo Hsu

Jui-Yuan Hsu

Chen-Yu Yu

Chih-Chi Wu

Wen-Shi Huang

Kuo-cheng Lin

Ming-Shi Tsai

Tsu-Liang Lin

Chin-Chu Huang

Yin-Yuan Chen

Chen-Chiang Su

Hung-Chang Hsieh

Lobato Lu

Ren-De Huang

Yung-Yu Chang

Kuang-Wei Chao

Yen-Chi Chou

Nai-Chien Chang

Jeng-Hung Lin

Min-Wen Kao

Jen-Chieh Peng

Hung Chang Hsieh

Min-Kuang Chang

Kuo-Ying Tsai

Chia-Kuan Liao

The disclosure provides a voltage regulator and a memory device. The voltage regulator includes a voltage generator and a bias circuit. The bias circuit dynamically adjusts a bias voltage based on a power saving mode signal of the memory device. The voltage generator adjusts a bias current of the voltage generator based on the bias voltage, wherein the bias current affects a slew rate of a target voltage. The voltage generator generates the target voltage to a driving circuit configured to drive a memory cell array in the memory device.

Voltage regulator and memory device

The memory device of the disclosure includes a fuse voltage generator, a fuse storage and a logic circuit. The fuse voltage generator generates a fuse voltage in response to an enable signal having a first logic level, and stop generating the fuse voltage in response to the enable signal having a second logic level. The fuse storage storages a setting data of the memory device. The fuse storage outputs the setting data in response to the fuse voltage. The logic circuit generates the enable signal in response to at least two operating signals.

Memory device

A voltage generating device includes a clock signal generator, a voltage regulator and a pump circuit. The clock signal generator generates a clock signal according to an enable signal. The voltage regulator generates and adjusts a first voltage according to a reference voltage and the enable signal. The pump circuit receives the clock signal, the first voltage and a second voltage, wherein the pump circuit performs a voltage pump operation to generate an output voltage based on the clock signal according to the first voltage and the second voltage. The output voltage equals to a summation of the first voltage and the second voltage.

Memory device, voltage generating device and voltage generating method thereof

A voltage regulator for providing a word line voltage is provided. The voltage regulator includes a voltage divider, a comparator, a boost circuit and a bypass transistor. The voltage divider is coupled between the word line voltage and a low reference voltage. The voltage divider includes resistive elements connected in series at intermediate nodes. The comparator provides an enable signal according to a divided voltage value on a divided intermediate node among the intermediate nodes. The boost circuit boosts the word line voltage in response to the enable signal. A source terminal of the bypass transistor is connected to a first intermediate node among the intermediate nodes. A drain terminal of the bypass transistor is connected to a second intermediate node among the intermediate nodes. The bypass transistor is turned-off in response to the control signal having an intermediate voltage value on the first intermediate node.

Voltage regulator for providing word line voltage

An antifuse circuit includes a current generator and an antifuse sense unit. The current generator has at least one electronic device. The antifuse sense unit is electrically connected to the current generator, and the antifuse sense unit has at least one copied electronic device. An electronic device specification of the at least one electronic device of the antifuse sense unit is equal to an electronic device specification of the at least one copied electronic device of the current generator. The current generator supplies a current to the antifuse sense unit that senses an antifuse.

Circuit for sensing antifuse of DRAMs

This invention provides a temperature sensor circuit and its operation method. The temperature sensor circuit includes a temperature sensor, a temperature comparator, a plurality of temperature sensor enable clocks with different clock cycles and a clock selection circuit. The temperature sensor detects a temperature of an Integrated circuit and sending a signal indicative of the temperature. The temperature comparator executes a comparison between the temperature of the Integrated circuit and a predetermined temperature setting upon receiving the signal indicative of the temperature and sending an output according to the comparison. Upon receiving the output, the clock selection circuit provides one of the temperature sensor enable clocks according to the output to enable the temperature sensor. The temperature detection cycle of the temperature sensor is thus adjustable to save the temperature sensor power.

Temperature sensor circuit and method thereof

A power providing circuit and a power providing method are provided. The power providing circuit includes at least one first charge pump circuit, at least one second charge pump circuit, a first control circuit, a signal latch, and a voltage detector. The first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The second charge pump circuit is configured to receive the first clock to generate the first pump voltage. The first control circuit is configured to provide the first clock to the first charge pump circuit and the at second charge pump circuit according to a power-on detection signal. The signal latch is coupled to the second charge pump circuit. The voltage detector is configured to receive an operation voltage and generate the power-on detection signal by detecting the operation voltage.

Power providing circuit and power providing method thereof

The present disclosure provides a dynamic random access memory (DRAM) and method for controlling the DRAM. The DRAM has a first operation mode and a second operation mode. The DRAM includes a control module and a connecting module. The connecting module includes an input/output (I/O) pad and a determining circuit. The I/O pad is configured to receive a first input signal. The determining circuit includes a detector and a first determining unit. The detector is configured to compare the first input signal to a reference signal so as to generate a first signal. The first determining unit is configured to receive the first signal and generate a first output signal according to the first signal. The control module is configured to control the DRAM being operated under the first operation mode or the second operation mode according to the first output signal.

Dynamic random access memory and method thereof

A memory device includes data receivers, voltage generators, and at least one pass gate. The data receivers include a first data receiver. The voltage generators is coupled to the data receivers and comprises a first voltage generator, in which the first voltage generator is configured to generate a first voltage signal for driving the first data receiver. The at least one pass gate is configured to be turned on under a first operation mode, to pass the first voltage signal generated from the first voltage generator of the voltage generators to at least one data receiver, other than the first data receiver, of the data receivers.

Memory device and method of operating the same

A semiconductor includes a first circuit, a second circuit, and a comparison circuit. The first circuit includes a first transistor. The first circuit is configured to output a first output. A second circuit includes a second transistor. The second circuit is configured to output a second output. A comparison circuit is coupled to the first circuit and the second circuit. The comparison circuit is configured to compare the first output and the second output to generate a comparison result, and to output the comparison result. The first transistor decays over a time interval and the first output changes from a first voltage value to a second voltage value over the time interval. The second transistor does not decay over the time interval and the second output of the second circuit maintains to be the third voltage value over the time interval.

Semiconductor device and operating method thereof

A voltage-stabilizing circuit includes a voltage-dividing module, a first stabilizing module and a second stabilizing module. The voltage-dividing module is configured to generate a plurality of reference voltages. The voltage-dividing module includes a plurality of resistors and a transistor unit. The transistor unit is coupled to the plurality of resistors and is configured to complementarily adjust resistances of the plurality of resistors. The first stabilizing module is coupled to the voltage-dividing module and is configured to generate a first stabilizing voltage. The first stabilizing voltage is equal to a middle one of the plurality of reference voltages. The second stabilizing module is coupled to the voltage-dividing module and is configured to generate a second stabilizing voltage. The second stabilizing voltage is equal to one of the plurality of reference voltages other than the middle one.

Voltage-stabilizing circuit, DRAM, and method for stabilizing a bit line voltage

The present disclosure provides a pump circuit comprising a plurality of first enabling modules. Each of the plurality of first enabling modules is configured to generate a first enable signal and includes a first voltage input, a first comparing unit, a first digital logic gate and a second digital logic gate. The first comparing unit is coupled to the first voltage input and is configured to compare a voltage of the first voltage input with a first reference voltage. The first digital logic gate is coupled to the first comparing unit and is configured to implement a logical operation. The second digital logic gate is coupled to the first digital logic gate and is configured to implement a logical negation. Each of the plurality of first enabling modules generates the first enable signal when the voltage of the first voltage input is less than the first reference voltage.

Pump circuit in a dram, and method for controlling an overall pump current

The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a storage area and a control device. The storage area includes a memory row. The control device is configured to selectively allow the memory row to be eligible for a row-hammer refresh according to temperature of the DRAM.

DRAM for storing data and method of operating the same

A system includes a fuse pump; a fuse that can be blown by the fuse pump; and a voltage source configured to provide a first voltage only if the fuse pump is enabled to blow the fuse, the fuse pump blowing the fuse when the first voltage serves as a supply voltage of the fuse pump. If the first voltage serves as a supply voltage of the fuse pump, a first consumed time is required to blow the fuse. If a second voltage, provided by the voltage source, were to be served as a supply voltage of the fuse pump, a second consumed time is required to blow the fuse. The first consumed time is less than the second consumed time.

System and method for blowing a fuse

A voltage switching device includes a receiver, a voltage controlled switch, a voltage detector and a first switch circuit. The voltage controlled switch is connected between an input data terminal and the receiver. The first voltage generator circuit is configured to provide a first voltage. The voltage detector is configured to output a first logic signal while detecting the first voltage higher than a predetermined voltage. The first switch circuit is connected between the first voltage generator circuit and the voltage controlled switch, the first switch circuit is turned on according to the first logic signal, so that the voltage controlled switch is turned on by the first voltage, and data are transmitted from the input data terminal to the receiver.

Growing community of inventors

Kaohsiung, Taiwan

Chih-Jen Chen