Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Other

Industrial Technology Research Institute

Chih-I Wu

I-Chih Ni

Jian-Zhi Huang

Yun-Yuan Wang

Yun-Hsuan Hsu

Chih-Hsiang Hsiao

Samuel C Pan

Ya-Ting Chang

Chien-Jung Huang

Chung-Chih Wu

Ken-Tsung Wong

Shih-Ming Lin

Pin-Hao Hu

Yu-Chung Lin

Ang-Sheng Chou

Ming-Han Tsai

Wen-Yi Hung

Hsin-Yu Chang

Hao-Wu Lin

Fu-Lung Chou

Shang-Yi Liu

Tsung-Chin Cheng

Hai-Ching Su

Fu-Chuan Fang

Yuan-Li Liao

Chi-Yen Lin

Tei-Hung Hou

Wei-Jiun Chen

Jin-Bin Yang

Shun-Siang Jhan

A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

Semiconductor device having 2D channel layer

A method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.

Semiconductor device with improved source/drain contact and method for forming the same

A semiconductor structure includes a semiconductor substrate, a gate structure, a source/drain structure, a contact, a dielectric layer, and a metal line. The gate structure is on the semiconductor substrate. The source/drain structure is adjacent to the gate structure. The contact lands on the source/drain structure. The dielectric layer spas the contact and the gate structure. The metal line extends through the dielectric layer to the contact. The metal line includes a liner over the contact, a magnetic layer over the liner, a graphene layer over the magnetic layer, and a filling metal over the graphene layer. The magnetic layer has a greater permeability coefficient than the filling metal.

Semiconductor device and method for forming the same

A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.

A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

Integrated circuit device and method for forming the same

A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.

Substrate having through via and method of fabricating the same

A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.

Semiconductor device and manufacturing method thereof

A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.

Deposition system and method using the same

A method and structure for providing high-quality transferred graphene layers for subsequent device fabrication includes transferring graphene onto a hydrophobic surface of a hydrophobic layer and performing a thermal treatment process. In various embodiments, a substrate including an insulating layer is provided, and a hydrophobic layer is formed over the insulating layer. In some examples, a graphene layer is transferred onto the hydrophobic layer. By way of example, the transferred graphene layer has a first carrier mobility. In some embodiments, after transferring the graphene layer, an annealing process is performed, and the annealed graphene layer has a second carrier mobility greater than the first carrier mobility.

Graphene transistor and related methods

The present invention discloses synthesis of 2,2'-disubstituted 9,9&#x2032;-spirobifluorene-based triaryldiamine. First, 2,2&#x2032;-diamino-9,9&#x2032;-spirobifluorene, a Pd-catalyst as auxiliary and aryl halide BX are provided, wherein X is selected from the group consisting of: Cl, Br and I, B comprises one of the following group: aryl moiety, hetero cycle, multiple fused ring, multiple fused ring with hetero atom(s). Next, a substitution reaction is performed to react the 2,2&#x2032;-diamino-9,9&#x2032;-spirobifluorene with the aryl halide BX to produce the 2,2&#x2032;-disubstituted 9,9&#x2032;-spirobifluorene-based triaryldiamines. In addition, the present invention discloses organic light emitting devices comprising hole transporting material comprising 2,2&#x2032;-bis(N,N-disubstituted amino)-9,9&#x2032;-spirobifluorenes.

Growing community of inventors

Taipei, Taiwan

Chih-I Wu