Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Hung Sun

Joung-Wei Liou

Po-Cheng Shih

Yi-Wei Chiu

Kuang-Yuan Hsu

Han-Ti Hsiaw

Shin-Yeu Tsai

Kuan-Cheng Wang

Jr-Yu Chen

Wen-Cheng Wu

Chia-Cheng Chou

Hui-Chun Yang

Tze-Liang Lee

Chung-Chi Ko

Chi-On Chui

Zhen-Cheng Wu

Chia Cheng Chou

Po-Hsien Cheng

In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.

Method of manufacturing semiconductor devices including forming an air gap based on removing a recessed sacrificial layer

A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.

Contact openings and methods forming same

Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.

Interconnect structure and method for forming the same

A method of forming a semiconductor device comprises forming a first etch stop layer over a substrate. The method also comprises forming a low-k dielectric layer comprising carbon over the first etch stop layer. The method further comprises forming an opening in the low-k dielectric layer. The method additionally comprises filling the opening with a conductive layer. The method also comprises performing a remote plasma treatment on the low-k dielectric layer and the conductive layer. The method further comprises forming a second etch stop layer over the treated conductive layer and the treated low-k dielectric layer.

Method of forming semiconductor device using remote plasma treatment

Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.

Method for forming semiconductor device structure

Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %.

A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom portion. A difference of C content in the top portion and the bottom portion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.

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Hsinchu, Taiwan

Chih-Hung Sun