Au Optronics Corporation

Amulaire Thermal Technology, Inc.

Chih-Hung Shih

Chih-Chun Yang

Ming-Yuan Huang

Ching-Huan Lin

Han-Tu Lin

Meng-Chieh Tsai

Ta-Wen Liao

Chih-Wen Chen

Hsiang-Lin Lin

Wei-Ming Huang

Ching-Sheng Cheng

Chia-Chi Tsai

Kuo-Lung Fang

Ren-Wei Liao

Kuan-Chun Huang

Chih-Jen Hu

Yu-Cheng Chen

Sheng-Chao Liu

Maw-Song Chen

Pei-Ming Chen

Yi-Chen Chiang

Tsan-Chun Wang

Chi-Mao Hung

Yao-Jen Hsieh

Chih-Hung Lin

Tze-Yang Yeh

Feng-Yuan Gan

Yu-Hsuan Li

Syuan-Ling Yang

Chin-Yueh Liao

Cho-Yan Chen

Ken-Ming Chen

Shiun-Chang Jan

Ya-Ting Hsu

Yi-Hui Li

Shih-Chyuan Fan-Jiang

Tzu-Hsuan Wang

Tzu-Wei Ho

En-Hung Liu

Ming-Yao Tsai

Yi-Hsueh Lin

Kuo-Sheng Tsao

An IGBT module with a heat dissipation structure and a method for manufacturing the same are provided. The IGBT module with a heat dissipation structure includes a layer of IGBT chips, a bonding layer, a thick copper layer, a thermally-conductive and electrically-insulating layer, and a heat dissipation layer. A portion of the thermally-conductive and electrically-insulating layer is made of a polymer composite material, and a remaining portion of the thermally-conductive and electrically-insulating layer is made of a ceramic material. The thick copper layer is bonded onto the thermally-conductive and electrically-insulating layer by hot pressing. A fillet is formed at a bottom edge of the thick copper layer, and the bottom edge of the thick copper layer is embedded into the thermally-conductive and electrically-insulating layer.

IGBT module with heat dissipation structure and method for manufacturing the same

Disclosed herein is a parallax barrier including a first substrate, a second substrate and a liquid crystal layer disposed between the first and the second substrates. A plurality of first strip electrodes and a plurality of second strip electrodes are arranged on the first substrate, whereas a plurality of third electrodes and a plurality of fourth electrodes are arranged on the second substrate. Each of the third electrodes has a step-shaped first portion and each of the fourth electrodes has a step-shaped second portion.

Method for forming autostereoscopic image

A first display zone and a second display zone are displayed based on a first light source group, which corresponds to a first voltage data signal; and then the second display zone and a third display zone are displayed based on light for a second light source group, which corresponding to a second voltage data signal. The first light source group and the second light source group illuminate the display zones alternatively. Each display zone is fed with either a first data voltage signal or a second data voltage signal. While the first data voltage signal is updating each display zone in sequence, the second data voltage signal starts updating the first display zone when the first voltage signal is updating the third display zone.

Stereoscopic display device and method for driving a stereoscopic display that updates a plurality of display zones

A liquid crystal display panel includes a substrate, gate lines, data lines, pixel electrodes, an insulating layer, patterned common electrodes and connection lines. Each pixel electrode includes a transparent electrode. The insulating layer covers the pixel electrodes. The patterned common electrodes are disposed on the insulating layer. Each patterned common electrodes includes a plurality of electrode branches, and at least one slit disposed between two adjacent electrode branches. The patterned common electrode includes a transparent electrode. The connection line is disposed on the insulating layer, and each connection line is in contact with and electrically connects to the patterned common electrodes of two adjacent sub-pixel regions.

Liquid crystal display panel

A method of displaying a three-dimensional image is disclosed. The method includes the steps of receiving a left-eye gray level image array and a right-eye gray level image array; converting the left-eye gray level image array and the right-eye gray level image array into a left-eye luminance image array and a right-eye luminance image array respectively; receiving a left-eye compensation array; adjusting the right-eye luminance image array in accordance with the left-eye luminance array and the left-eye compensation array; converting the adjusted right-eye luminance image array into an adjusted right-eye gray level image array; displaying the adjusted right-eye gray level image array.

Method of displaying a three-dimensional image

A stereoscopic display is proposed. A first display zone and a second display zone are displayed based on light for a first light source group, in response to a first data voltage signal fed to the first display zone and the second display zone, and to a second data voltage signal fed to a third display zone. The second display zone and the third display zone are displayed based on light for a second light source group, in response to the second data voltage signal fed to the first display zone, and to the first data voltage signal fed to the second display zone and the third display zone. The first display zone and the second display zone are displayed based on light from the first light source group, in response to the second data voltage signal fed to the first display zone and the second display zone, and to the first data voltage signal fed to the third display zone. The second display zone and the third display zone are displayed based on light from the second light source group, in response to the first data voltage signal fed to the first display zone, and to the second data voltage signal fed to the second display zone and the third display zone.

Stereoscopic display

Liquid crystal parallax barrier with strip-shaped and step-shaped electrodes and application thereof

A pixel structure includes a substrate, a gate line and a gate electrode disposed on the substrate, an insulating layer covering the substrate, a semiconductor layer disposed on the insulating layer, a data line, a source electrode, and a drain electrode which are disposed on the insulating layer and the semiconductor layer, a planarization layer disposed on the data line, the source electrode, and the drain electrode, and a pixel electrode disposed on the planarization layer. The planarization layer has a through hole exposing the drain electrode. The pixel electrode is electrically connected to the drain electrode via the through hole and includes an opaque main electrode and a plurality of transparent branch electrodes disposed on the planarization layer. One end of each transparent branch electrode is electrically connected to the opaque main electrode.

Pixel structure and method of making the same

A three-dimensional display includes a display panel having a plurality of first pixels arranged in the odd row, and a plurality of second pixels arranged in the even row. Each first pixel has a first and a second transparent regions and a first semiconductor pattern. Each second pixel has a third and a fourth transparent regions and a second semiconductor pattern. In any two adjacent first and second pixels, the first and the third transparent regions are mirror images of each other, and the second and the fourth transparent regions are mirror images of each other. In the adjacent first and second pixels arranged in any two rows, the loss of the light transmittance at any position along the row direction due to overlapping of the first semiconductor and the first transparent region and overlapping of the second semiconductor and the fourth transparent region remains unchanged.

Three-dimensional display

A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Display device having slim border-area architecture and driving method thereof

A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate. The insulating patterns are isolated from each other by the first conductive pattern layer. The metal-line region includes an insulating multilayer formed on the substrate and a conductive pattern layer formed on the insulating multilayer. Several isolated zones are formed by the conductive pattern layer on the surface of the insulating multilayer.

Display panel and method for manufacturing the same

This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Pixel designs of improving the aperture ratio in an LCD

An MVA LCD device includes a first alignment region, a second alignment region, a third alignment region, and a fourth alignment region. The liquid crystal molecules disposed in the first alignment region have a first aligning direction, and the azimuth angle of the first aligning direction is substantially between 70 and 110 degrees. The liquid crystal molecules disposed in the second alignment region have a second aligning direction, and the azimuth angle of the second aligning direction is substantially between 160 and 200 degrees. The liquid crystal molecules disposed in the third alignment region have a third aligning direction, and the azimuth angle of the third aligning direction is substantially between 250 and 290 degrees. The liquid crystal molecules disposed in the fourth alignment region have a fourth aligning direction, and the azimuth angle of the fourth aligning direction is substantially between &#x2212;20 and 20 degrees.

Multi-domain vertical alignment liquid crystal display device and pixel structure thereof

A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate.

Methods of manufacturing master, pixel array substrate and electro-optical device

The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.

Shift register with embedded bidirectional scanning function

Growing community of inventors

Hsinchu, Taiwan

Chih-Hung Shih