United Microelectronics Corp.

Au Optronics Corporation

United Semiconductor Corp.

Chih-Hung Lin

Yu-Cheng Chen

Yi-Hui Li

Gary Y Hong

Joe Ko

Maw-Song Chen

Ping-Chia Shih

Hwi-Huang Chen

Chi-Cheng Huang

Hsiang-Chen Lee

Chuan-Sheng Wei

Chih-Ming Wang

Wu-Liu Tsai

Tsan-Chun Wang

Yau-Kae Sheu

Robin Lee

Chun-Sung Huang

Chau-Shiang Huang

Chen-Chiu Hsue

Ching-Huan Lin

Hsiang-Lin Lin

Wei-Ming Huang

Ming-Tsung Tung

Chih-Hung Shih

Che-Chia Chang

Anchor Chen

Sheng-Chao Liu

Jung-Ching Chen

Jih-Wei Liou

Chin-Hung Liu

Tung-Huang Chen

Chien-Ming Lin

Yen-Chang Chen

Alex Hsieh

Jih-Wen Chou

Chun-Ming Wu

A manufacturing method of pixel structure includes forming a first conductive layer on a substrate and forming a first insulation layer thereon; forming a second conductive layer on the first insulation layer; forming a second insulation layer on the second conductive layer; forming a semiconductor layer on the second insulation layer above the gate; forming a third conductive layer on the second insulation layer, wherein the gate, the semiconductor layer, the source, and the drain together constitute a thin film transistor, and the first electrode, the second electrode, and the third electrode together constitute a capacitor; forming a third insulation layer on the third conductive layer; and forming a pixel electrode on the third insulation layer, the pixel electrode being electrically connected to the drain.

Manufacturing method of pixel structure

An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.

Fabricating method of array structure

Array structure and fabricating method thereof

A display panel having a display region and a non-display region is provided. The display panel includes a plurality of pixel structures in the display region, and each pixel structure includes a scan line, a data line, a first active device, a pixel electrode, a first insulating layer, a capacitor electrode, and a second insulating layer. The first active device includes a first gate, a first channel, a first source, and a first drain. The second insulating layer covers the first insulating layer and the capacitor electrode and is located between the capacitor electrode and the first drain. At least one driving circuit is disposed in the non-display region and includes at least one second active device. Hence, a relatively thin insulating layer can be disposed between the capacitor electrode and the drain to reduce the area of the capacitor region and to achieve a desired aperture ratio.

Driving circuit and display panel having the same

A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Pixel structure having storage capacitance of the capacitor

A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.

Non-volatile memory cell and fabricating method thereof

A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.

SONOS non-volatile memory cell and fabricating method thereof

This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Pixel designs of improving the aperture ratio in an LCD

An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.

Active device, pixel structure and display panel

A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.

Pixel array

A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.

Method for forming semiconductor structure and method for forming memory using the same

A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

High-voltage device structure

A semiconductor substrate has at least one active area and a STI surrounding the active area. An N-well and an adjacent P-well are formed in the active area. A dummy gate is formed atop the border between the N-well and the P-well, while simultaneously forming gates for other MOS transistors on the semiconductor substrate. A spacer is formed on the periphery of each gate. Finally, an N-type ion implantation process and a P-type ion implantation process are performed to form a cathode and an anode for the silicon controlled rectifier device in the P-well and the N-well between the STI and the dummy gate.

Method for making a thyristor

A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Fabrication method for a two-bit flash memory cell

A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

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Taoyuan County, Taiwan

Chih-Hung Lin