Intel Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Hung Chung

James P Kardach

Jason Ziller

Edward Thomas Grochowski

Shyh-An Chi

Gregory Scott Mathews

Derek T Bachand

John William Horigan

Borys S Senyk

Tosaku Nakanishi

George Thangadurai

Gururaj Shamanna

Ravi Eakambaram

This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.

Dynamic voltage and frequency management in integrated circuits

An apparatus and method for reducing power consumption in a processor front end are provided. The processor includes an instruction cache, a TLB, and a branch predictor. For sequential code execution, the instruction cache is disabled unless the next instruction fetch will cross a cache line boundary, thus reducing unnecessary accesses to the instruction cache. The TLB is disabled unless the next instruction fetch will cross a page boundary, thus reducing unnecessary TLB look-ups. For code branching, the branch predictor is configured to include, for each target address, an indication of whether the target address is in the same page as the corresponding branch address. When a branch occurs so as to cause access to a given entry in the branch predictor, the TLB is disabled if the target address is in the same page as the branch address.

Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end

A method and apparatus for avoiding tag compares when writing to a cache. In a cache hierarchy, location information of the cache entries are linked and supplied to the other caches, during caching of the data from memory. When the processor is ready to update the content of the memory location, the location information loaded into a write buffer allows the write buffer to update the cache(s), without the need for tag comparisons to determine if particular entries are present. The avoidance of the tag compare operation during cache update saves a clock cycle, so that overall processor performance is improved.

Avoiding tag compares during writes in multi-level cache hierarchy

In accordance with an embodiment of the invention, unused data bits are set to a preferred value, either zero or one, depending on the circuit used to read the data. With the unused data bits set to the preferred value the precharge is not discharged during the data read operation. Not discharging the precharge allows power to be saved in the subsequent precharge and read operation.

Power conservation during memory read operations

A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

Method and apparatus for maintaining cache coherency in an integrated

A computer system is provided for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

System, apparatus and method for managing power in a computer system

A microprocessor includes the capability to service at least one debug exception and an I/O trap generated during execution of a single instruction. After executing each instruction, the microprocessor determines whether a debug exception and an I/O trap occurred. If at least one debug exception and an I/O trap exist, then the microprocessor determines an active status for the debug exception. The microprocessor stores the contents of internal registers, constituting a state of the microprocessor, to memory, and latches a breakpoint status for the debug exception in a public debug status register. The breakpoint status is preserved by copying the breakpoint status to a private debug status register. The microprocessor services the I/O trap by executing a SMM handler, an upon returning from the SMM handler, the state of the microprocessor is restored. If the I/O trap serviced requires instruction restart, then the state of the microprocessor is adjusted to re-execute the instruction. The microprocessor copies the breakpoint status, stored in the private debug status register, to the public debug status register when the I/O trap does not require instruction restart. The debug exception is subsequently serviced by executing an INT1 handler.

Method and apparatus for servicing simultaneous I/O trap and debug traps

A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

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Saratoga, CA, United States of America

Chih-Hung Chung