Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Mediatek Corporation

Chih Hsuan Wang

Hao-Yi Tsai

Tin-Hao Kuo

Po-Yuan Teng

Teng-Yuan Lo

Ching-Yao Lin

Hung-Jui Kuo

Hui-Jung Tsai

Jr-Jung Lin

Chih-Han Lin

Chao-Cheng Chen

Shih-Yao Lin

Chen-Yu Wu

Shih-Jung Chiu

Chi-Wei Yang

Pei-Hsiu Wu

Yun Ting Chou

Yen Ping Wang

Hao Sheng Hsu

Wen Wang Ke

Heng Chieh Chien

Yi Shiau Chen

Ming Hsi Tseng

Fu Jung Chen

An alignment holder for holding a composite specimen includes a holder body and a positioning mechanism. The holder body is configured to clamp a first side of the composite specimen therein. The positioning mechanism is movably engaged with the holder body. The positioning mechanism is configured to lean against a second side of the composite specimen and move relatively to the holder body for adjusting a clamping position of the composite specimen clamped by the holder body.

Alignment holder and testing apparatus

Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Gate structure with desired profile for semiconductor devices

A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Dummy FIN profile control to enlarge gate process window

A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

Semiconductor package and manufacturing method thereof

A method for manufacturing a semiconductor package includes the following steps. A semiconductor process is performed to form an encapsulated semiconductor device, wherein the encapsulated semiconductor device comprises an encapsulating material and a semiconductor device encapsulated by the encapsulating material. A testing apparatus including a holder body, a positioning mechanism and a force applying bar is provided. The encapsulated semiconductor device is clamed by the holder body. A clamping position of the encapsulated semiconductor device is adjusted by the positioning mechanism. The positioning mechanism is removed. A predetermined force is applied to a part of the encapsulated semiconductor device exposed by the holder body by the force applying bar. If the encapsulated semiconductor device is failed by the predetermined force, a process parameter of the semiconductor process is modified to form a modified encapsulated semiconductor device.

Method for manufacturing a semiconductor package and method for testing bonding strength of composite specimen

A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.

An alignment holder for holding and testing a composite specimen includes a holder body, a supporter, and a positioning mechanism. The holder body is configured to clamp a first side of the composite specimen. The supporter is detachably connected to a lower part of the holder body for supporting a lower surface of the composite specimen. The positioning mechanism is configured to lean against a second side of the composite specimen and move relatively to the holder body for adjusting a clamping position of the composite specimen clamped by the holder body.

Alignment holder, testing apparatus and method for manufacturing a semiconductor package

Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.

Method of detecting photoresist scum, method of forming semiconductor package and photoresist scum detection apparatus

A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.

A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.

A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.

An adaptive tuning method comprises the steps of: obtaining a statistical result; determining whether an adaptive tuning procedure is to be performed in accordance with the statistical result; obtaining reference information of the first wireless module; and performing the adaptive tuning procedure in accordance with the reference information.

Adaptive tuning method and apparatus for a combo wireless system

A method for controlling an OPU and an optical data access apparatus are provided. A signal generator is configured to generate a servo signal in response to data access. A comparator is configured to compare a threshold level and the servo signal, and generate a control level if a level of the servo signal against the threshold level when the OPU is controlled. An adjustment unit is configured to adjust a control signal according to the control level. The OPU is controlled according to the adjusted control signal.

Optical data access apparatus and method thereof

A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically active dopant therein. A second of the gate electrodes is formed of the first gate electrode material having less than the first concentration of the electrically active dopant therein, and formed at least partially as an alloy with a second gate electrode material. The semiconductor product may be formed with enhanced efficiency.

Selective doping and thermal annealing method for forming a gate electrode pair with different work functions

A dynamic bias circuit for an RF amplifier is provided to overcome the drawbacks of conventional bias circuits. The dynamic bias circuit of the present invention is best used for an RF amplifier having an FET amplifying transistor. It automatically raises the DC bias point as the input power increases. As a result, the saturation of output power in the pinch-off region can be avoided. This dynamic bias circuit not only improves the operating characteristics of the RF amplifier, such as high operating efficiency and high-linearity output power, but also consumes zero power in its internal circuitry. Furthermore, it has a simple circuit structure with very few circuit components and a reduced chip area. It can thus be easily integrated into an amplifier to achieve a cost reduction.

Growing community of inventors

Hsinchu County, Taiwan

Chih Hsuan Wang