Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih Hsuan Cheng

Chih-Teng Liao

Tzu-Chan Weng

Yi-Wei Chiu

Yu-Li Lin

Chih-Shan Chen

Li-Te Hsu

Jui Fu Hsieh

Chia-Chi Yu

Chia-Cheng Tai

Yan-Ting Shen

A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

Source and drain structure with reduced contact resistance and enhanced mobility

A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

Semiconductor device and method

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

Fin field-effect transistor device and method of forming

A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Method of manufacturing a semiconductor device including etching polysilicon

A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

Method of manufacturing a semiconductor device and a semiconductor device

A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

Doping through diffusion and epitaxy profile shaping

A method includes etching a substrate to form a first semiconductor strip. A first dummy gate structure is formed over a first channel region of the first semiconductor strip. First and second recesses are etched in the first semiconductor strip on either side of a first dummy gate. An intermetallic doping film is formed in the first recess and the second recess. A dopant of the intermetallic doping film is diffused into the first semiconductor strip proximate the recesses. Source/drain regions are epitaxially grown in the recesses. A device includes semiconductor strips and a plurality of gate stacks. A first epitaxial source/drain region is interposed between a first two of the plurality of gate stacks. A first dopant diffusion area surrounds the first epitaxial source/drain region and has a first concentration of a first dopant greater than a second concentration of the first dopant outside the first dopant diffusion area.

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Houlong, Taiwan

Chih Hsuan Cheng