Gemtek Technology Co., Ltd.

Industrial Technology Research Institute

Chih-Hsu Yen

Hung-Wen Chen

Fu-Ming Tien

Fan-Di Jou

Wen-Yu Peng

Chun-Lung Lin

Tian-Jian Wu

Yuh-Sheng Chan

Tsung-Hsi Pai

A power bank has a station and a plurality of battery modules. When the battery modules are stacked on the station, rechargeable batteries of the battery modules are electrically connected in parallel. When a charging port of the station is electrically connected to an external power supply, a charging-discharging control circuit of the station receives electric energy from the external power supply via the charging port and uses the received electric energy to charge the rechargeable batteries. When a discharging port of the station is electrically connected to an external electronic device, the charging-discharging control circuit transfers electric energy received from the rechargeable batteries to the external electronic device. Each of the battery modules is replaceable, and the total number of the battery modules of the power bank is adjustable.

Power bank with a plurality of stacked battery modules

A power bank has a station and a plurality of battery modules. Each of the battery modules can be positioned in a corresponding slot of the station in a pluggable way and is electrically connected to a charging-discharging control circuit of the station. When a main charging port of the station is electrically connected to a power supply, the charging-discharging control circuit receives electric power from the power supply via the main charging port and uses the received electric power to charge rechargeable batteries of the battery modules. When a main discharging port of the station is electrically connected to an electronic apparatus, the charging-discharging control circuit receives electric power from the rechargeable batteries of the battery modules so as to provide electric power to the electronic apparatus.

Power bank with a plurality of pluggable battery modules

An audio playing system has a first channel output device, a first equalizer, and a controller. The first equalizer is configured to adjust a received first channel audio signal with a set of first parameters of frequency response and output the adjusted first channel audio signal to the first channel output device in a first mode, and to adjust the received first channel audio signal with the a of second parameters of frequency response and output the adjusted first channel audio signal to the first channel output device in a second mode. In a test mode, the controller is configured to send a set of test audio signals to the first channel output device and to adjust the set of first parameters of frequency response and the set of second parameters of frequency response based on a plurality of pieces of received first confirmation signal.

Audio playing system

An audio playing system has a first channel output device, a first audio modulator and a controller. The first audio modulator is electrically coupled to the first channel output device and having a set of first modulation parameters, the first audio modulator configured to selectively modulate a first channel audio signal with the set of first modulation parameters and output the modulated first channel audio signal to the first channel output device. The controller is electrically coupled to the first channel output device and the first audio modulator, wherein in a test mode, the controller is configured to send a set of test audio signals to the first channel output device, to generate a set of first user parameters based on a plurality of pieces of first confirmation signal, and to adjust the set of first modulation parameters based on the set of first user parameters.

Audio playing system capable of automatically personally compensating

An audio playing system has a first channel output device, a first equalizer and a controller. The first equalizer is electrically coupled to the first channel output device and having a set of first parameters of frequency response, the first equalizer configured to adjust a first channel audio signal with the set of first parameters of frequency response and output the adjusted first channel audio signal to the first channel output device. The controller is electrically coupled to the first channel output device and the first equalizer, wherein in a test mode, the controller is configured to send a set of test audio signals to the first channel output device, to generate a set of first user parameters based on a plurality of pieces of first confirmation signal, and to adjust the set of first parameters of frequency response based on the set of first user parameters.

An audio playing system has a first channel output device, a first equalizer, a second channel output device, a second equalizer, a loudness adjusting button, and a controller. The first equalizer adjusts a first channel audio signal with a set of first parameters of frequency response and output it to the first channel output device. The second equalizer adjusts a second channel audio signal with a set of second parameters of frequency response and output it to the second channel output device. The loudness adjusting button generates a loudness instruction. The controller determines an upper limit of loudness based on the set of first parameters of frequency response and the set of second parameters of frequency response, and adjusts a loudness related to the first channel audio signal and a loudness related to the second channel audio signal based on the upper limit of loudness and the loudness instruction.

The disclosure provides a matrix transposing circuit for outputting a transposed N&#xd7;N matrix. The matrix transposing circuit includes: an input resister array with m&#xd7;N array; a memory having b storage blocks; an output register array with N&#xd7;m array. N, m, n, b are integer in power of 2, N can be completely divided by m and n, and N=n&#xd7;m&#xd7;b. The matrix is divided into multiple sub-matrixes with m&#xd7;n array to form Y matrix. Each of sub-matrixes is correspondingly stored to the b storage blocks. The input resister array has a first shifting direction to receive entry data and a second shifting direction to output data to the b storage blocks. The output resister array has a first shifting direction to read data from the b storage blocks and a second shifting direction to output the transposed matrix.

Matrix transposing circuit

An electronic device assembly structure comprises two electronic devices and at least one connection module. Each electronic device includes a body and at least one USB located on the body. The connection module connects to the two electronic devices and includes an electric connection unit and a fastening unit. The electric connection unit is electrically inserted into the USBs of the two electronic devices. The fastening unit fastens the bodies of the two electronic devices together in an integrated manner.

Electronic device assembly structure

A method for frame memory compression divides each of a plurality of image frames in a frame memory into a plurality of blocks and quantizes a plurality of pixel values inside each block according to a predefined parameter, thereby generating a quantized block and a plurality of removed bits from the binary representation of the plurality of pixel values. A predictor is used to produce a residual block for the quantized block. A variable length encoder takes the residual block as an input and produces a coded bitstream. A packing unit is used to take the coded bitstream and the number of removed bits generated by the quantizer as inputs, so as to produce an entire codeword sequence of the block that meets a target bit rate by using a structure called group of blocks (GOB) to flexibly share available spaces of the blocks in the same GOB.

Method and apparatus for frame memory compression

Disclosed are a semi-sequential Galois field GF(2) multiplier and the method thereof. The GF(2) multiplier comprises two ground field multipliers over GF(2), at least a constant multiplier, and multiple GF(2) adders. The high-order and low-order elements from a composite field GF((2)) for one operand of one GF(2) multiplication are inputted in parallel into the two ground GF(2) multipliers, respectively. The high-order and low-order elements from the composite field of another operand of the GF(2) multiplication are sequentially inputted into the two ground GF(2) multipliers. As such, multiple partial products are generated. The constant multiplication and additions are performed on the multiple partial products through the constant multiplier and the GF(2) adders. This generates a high-order element and a low-order element of the composite field GF((2)). After mapping these two elements of GF((2)) back to GF(2), the GF(2) multiplication is done.

Semi-sequential Galois Field multiplier and the method for performing the same

Disclosed is a low-latency method and apparatus of GHASH operation for authenticated encryption Galois Counter Mode (GCM), which simultaneously computes three interim values respectively yielded from the additional authenticated data A, the ciphertext C, and the hash key H defined in the GCM. Then, the output of the GHASH operation may be derived. Assuming that A has m blocks and C has n blocks, this disclosure performs the GHASH operation with max {m,n}+1 steps. The input order for the additional authenticated data A and the ciphertext C may be independent. A disordered sequence for the additional authenticated data A and the ciphertext C may also be accepted by this disclosure. This allows the applications in GCM to be more flexible.

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Hsinchu, Taiwan

Chih-Hsu Yen