Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Industrial Technology Research Institute

Chih-Hsing Yu

Chia-Shiung Tsai

Yeur-Luen Tu

Kuo-Chi Tu

Dahcheng Lin

Min-hwa Chi

Chih-Yang Pai

Yuan-Hung Liu

Arbee L Chen

Cheng-Yao Ni

Chih-Chin Liu

Yu-Shen Chen

Hsiao-Ying Yang

Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within the dynamic random access memory (DRAM) cell structure to thus provide a patterned hard mask layer and a patterned capacitor plate layer which define a via. The patterned capacitor plate layer is then isotropically etched and recessed beneath the patterned hard mask layer, while forming from the via an enlarged via. There is then formed over the patterned hard mask layer, and completely filling the enlarged via, an inter-metal dielectric (IMD) layer. There is then anisotropically etched the blanket inter-metal dielectric (IMD) layer to form a patterned inter-metal dielectric (IMD) layer which in part defines a biaxially extended via at the location of the via, wherein portions of the patterned inter-metal dielectric (IMD) layer which define the biaxially extended via passivate sidewall portions of the isotropically etched patterned capacitor plate layer.

Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (DRAM) cell structure

A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are in turn defined in a group of composite insulator layers. A first fin type capacitor opening is formed by selectively creating lateral recesses in first type insulator layers, exposed in a first capacitor opening in the composite insulator layers, while an adjacent, second fin type capacitor opening is formed by selectively creating lateral recesses in second type insulator components, exposed in a second capacitor opening located in the same composite insulator layers. Portions of the lateral recesses in the first and second fin type capacitor openings overlay, allowing intertwined or alternate, storage node structures to be realized, thus reducing the space needed for the capacitor structure. The horizontal features of the fin shaped storage node structure, located in the lateral recesses, result in increased capacitor surface area when compared to counterparts fabricated without the lateral recess component.

Method of fabricating a DRAM device featuring alternate fin type capacitor structures

A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.

Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer

A method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning is deacribed. A plurality of capacitor node contact junctions and a bit line junction are provided in a semiconductor substrate. A node contact plug is formed through a first insulating layer to each of the capacitor node contact junctions. A bit line contact plug is formed to the bit line junction. Openings are etched through a second insulating layer to each of the node contact plugs. A polysilicon layer is conformally deposited within the openings and then recessed below the top of the openings wherein each of the polysilicon layers forms a bottom plate electrode of a capacitor. A capacitor dielectric layer is formed overlying the bottom plate electrodes and the second insulating layer. A polysilicon layer is deposited overlying the capacitor dialectic layer and patterned to form top capacitor plates overlying each of the bottom plate electrodes to complete the capacitors. An opening is etched through a third and the second insulating layers between the capacitors to the bit line contact plug and filled with a conducting layer to form a bit line to complete fabrication of a DRAM with CUB cell in an integrated circuit device.

Method of fabricating capacitor-under-bit line (CUB) DRAM

Within a first of a pair of methods for forming a memory cell structure there is employed a sacrificial spacer layer formed adjacent a capacitor structure and subsequently stripped therefrom to provide an air gap void interposed between a bitline stud layer and the capacitor structure. Within a second of the pair of methods for forming a memory cell structure there is employed a topographically variable thickness masking layer as a self aligned mask layer for forming a patterned capacitor plate layer from a topographic blanket capacitor plate layer. The methods provide for readily forming the memory cell structure with enhanced performance.

Methods for forming memory cell structures

A new method is provided for the creation of the bit line contact plug. CUB capacitors typically are located adjacent to the bit line contact plug, a parasitic capacitance therefore exists between the CUB and the contact plug. Typical interface between the CUB and the bit line contact plug consists of a dielectric. By creating an air gap that partially replaces the dielectric between the CUB and the bit line contact plug, the dielectric constant of the interface between the bit line and the CUB is reduced, thereby reducing the parasitic coupling between the bit line contact plug and the CUB. This enables the creation of CUB capacitors of increased height, making the CUB and the therewith created DRAM devices better suited for the era of sub-micron device dimensions.

Method to reduce bit line capacitance in cub drams

Within a method for forming a contact via there is provided a substrate having formed thereover a pair of topographic structures separated by a contact region formed within the substrate. There is then formed upon the substrate and the pair of topographic structures a blanket conformal isolation layer which has formed thereupon a blanket variable thickness masking layer formed thicker over the pair of topographic structures than interposed between the pair of topographic structures. The blanket variable thickness masking layer and the blanket conformal isolation layer are then completely etched through interposed between, but not over, the pair of topographic structures to thus form the contact via. The method is useful for forming bitline contact vias within memory cell structures.

Method for forming a bitline contact via within a memory cell structure

A method of planarizing the peripheral circuit region of a DRAM. A first oxide layer and a silicon nitride layer are sequentially formed over a substrate. A plurality of polysilicon plugs are formed within the crown-shaped capacitor region of the DRAM. A patterned second oxide layer is formed over the silicon nitride layer. A conformal doped amorphous silicon layer is formed over the exposed surface of the crown-shaped capacitor region and the peripheral circuit region of the DRAM. A photoresist layer is formed over the crown-shaped region and then a nitrogen implant is carried out to form a silicon oxy-nitride barrier layer. A chemical-mechanical polishing is carried out to separate the various lower electrodes. The photoresist layer and the second oxide layer within the crown-shaped capacitor region are removed. Hemispherical silicon grains are grown on the exposed surface of the doped amorphous silicon layer. A dielectric layer and an upper electrode layer are sequentially formed over the hemispherical silicon grains on the doped amorphous silicon layer.

Method of planarizing peripheral circuit region of a DRAM

A process of forming a capacitor under bit line (CUB), structure, for a DRAM device, highlighted by simultaneous definition of the storage node structures, and a bit line contact structure, and by simultaneous definition of the capacitor top plate, and the bit line opening, has been developed. The process features forming a narrow diameter bit line contact hole, exposing a underlying polysilicon plug structure, while forming wider diameter, capacitor openings, to other underlying polysilicon plug structures. Polysilicon deposition, followed by a chemical mechanical polishing procedure, results in the simultaneous definition of the storage node, and bit line contact structures. Subsequent processing, comprising polysilicon and silicon oxide depositions, followed by an anisotropic RIE procedure, allow the definition of the capacitor structure to be defined simultaneously with the formation of a bit line opening.

Method of fabricating a capacitor under bit line structure for a dynamic random access memory device

A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor opening, needed to accommodate a capacitor structure with increased vertical dimensions, via selective removal of the top portions of the polysilicon plug structures exposed in the capacitor openings. The depth of a subsequent bit line contact hole, opened to a non-truncated polysilicon plug structure, is therefore not increased as a result of the increase capacitor depth, thus not resulting in an increased aspect ratio for the dry etched, narrow diameter bit line contact hole.

Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole

A method of fabricating a twin-tub capacitor is described in which a dielectric layer is defined to form multiple column structures, followed by forming a conductive layer over the column structures. The conductive layer on the top surface of the column structures are removed by chemical mechanical polishing to isolate each capacitor. The column structures are further removed to form a twin-tub capacitor.

Fabrication method of a twin-tub capacitor

A method of forming a capacitor. A substrate comprises a cell array area and a peripheral area. A dielectric layer is formed on the substrate. The covering layer is formed on the dielectric layer. The contact electrode is formed through the dielectric layer and the covering layer. The first oxide layer is formed over the substrate. A portion of the first oxide layer is removed to form an opening, which exposes the contact electrode. A conformal preserve layer is formed over the substrate. A second oxide layer is formed over the substrate. A portion of the second oxide layer in the cell array area is removed to form an opening, which exposes the contact electrode. A conformal first conductive layer is formed over the substrate to cover the second oxide layer and the opening. A third oxide layer is formed over the substrate to cover the first conductive layer and fill the opening. A planarization step is performed to remove the third oxide layer, the first conductive layer, and the second oxide layer until the preserve layer in the peripheral area is exposed. The third oxide layer and the second oxide layer in the cell array area are removed to expose conductive layer. A selective hemispherical grained silicon layer and a dielectric film are formed in sequence over the exposed conductive layer. A second conductive layer is formed over the substrate to fill the opening.

Method of fabricating capacitor capable of maintaining the height of the

A video indexing and query execution system includes a processor which indexes video clips by: (a) identifying each symbol of one or more graphical icons in each frame of each video clip, (b) determining the horizontal, vertical and temporal coordinates of each symbol of the identified graphical icons, and (c) constructing a database for each identified symbol of the graphical icons. The processor converts a video query from graphical form to string form by: (a) receiving a video query specifying the vertical, horizontal and temporal coordinates of a graphical icon to be matched in at least one frame to be retrieved, and (b) constructing a normal 3-D string from the video query indicating the distance between each symbol of each icon in the video query in each direction. The processor also executes a video query on a video database by: (a) identifying only those video clips of the database whose signatures contain the signature of the executed video query, (b) for each of the identified video clips: (b1) constructing a 1-D list for each of the horizontal, vertical and temporal directions, comprising a plurality of sets of symbols of icons contained in video query, each set containing a permutation of symbols of the icons which satisfy the video query in the respective direction of the 1-D list, and (b2) forming the intersection of the three 1-D lists, and (c) identifying the portions of the video clips, indicated by a corresponding set contained in an intersection set of at least one of the identified video clips, as satisfying the video query.

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Hsin-Chu, Taiwan

Chih-Hsing Yu