Taiwan Semiconductor Manufacturing Comp. Ltd.

National Central University

Chih-Hsin Ko

Clement Hsingjen Wann

Cheng-Hsien Wu

Yi-Jing Lee

Wen-Chin Lee

Chung-Hu Ke

You-Ru Lin

Yee-Chia Yeo

Ding-Kang Shih

Hau-Yu Lin

Chih-Hao Chang

Hung-Wei Chen

Chenming Hu

Cheng-Tien Wan

Tsung-Lin Lee

Sung-Li Wang

Jeff J Xu

Feng Yuan

Chun Hsiung Tsai

Chao-Ching Cheng

Hsin-Chih Chen

Chia-Ming Hsu

Yao-Tsung Huang

Neng-Kuo Chen

Ching-Feng Fu

Sey-Ping Sun

Gin-Chen Huang

Yi-An Lin

Chen-Feng Hsu

Meng-Chun Chang

Shu-Han Chen

Ya-Yun Cheng

Ji-Yin Tsai

Ta-Ming Kuan

Yu-Ming Lin

Chi-Wen Liu

Li-Chun Tien

Shahaji B More

Po-Hsiang Huang

Sheng-Hsiung Chen

Fong-yuan Chang

Chun-Chieh Lin

Chien-Chao Huang

Chung-Hu Ge

Chi-Feng Huang

Chewn-Pu Jou

Yen-Ming Chen

Chih Chieh Yeh

Huan-Neng Chen

Fu-Lung Hsueh

Ming-Hsi Yeh

Huan-Just Lin

Liang-Yin Chen

Chan-Lon Yang

Chun-Chieh Lu

Kuang-Hsin Chen

Xiong-Fei Yu

Chun-Hung Lee

Chandrashekhar Prakash Savant

Shih-Ting Hung

Kai-Tai Chang

Hui-Cheng Chang

Hao-Hsiung Lin

Yu-Chan Yen

Ta-Chun Ma

Yi-Shan Chen

Po-Wen Chiu

Wei-Chieh Chen

Ruey-Hsin Liu

Hun-Jan Tao

I-Sheng Chen

Yasutoshi Okuno

Kuo-Feng Yu

Chih-Chang Cheng

Shih-Fen Huang

Jen-Inn Chyi

Andrew Joseph Kelly

Fu-Yu Chu

Baw-Ching Perng

Yi-Chun Huang

Shou Zen Chang

Yi-Jing Li

Syun-Ming Jang Jang

Tze-Liang Lee

Jyu-Horng Shieh

Pang-Yen Tsai

Shao-Ming Yu

Yen-Ping Wang

Yi-Tang Lin

Da-Wen Lin

Wei-Sheng Yun

Min-Hwa Chi

Bor-Wen Chan

Ju-Wang Hsu

Bor Chiuan Hsieh

Hong-Nien Lin

Wen Han Hung

Lawrence Chiang Sheu

Che-Chih Hsu

Chinyu Su

The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.

FinFET device having a channel defined in a diamond-like shape semiconductor structure

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Method of manufacturing a semiconductor device

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Method for fabricating a strained structure and structure formed

An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Integrated circuit fin structure

Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.

Manufacturing method for semiconductor structure having a plurality of fins

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Semiconductor device and manufacturing method thereof

A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.

Integrated circuit fin structure manufacturing method

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Wrap-around contact on FinFET

A field effect transistor (FET) device includes a substrate, a gate structure over the substrate, a channel region under the gate structure, the channel region including a first semiconductor material, and a second semiconductor material interposed between the first semiconductor material and the substrate. The second semiconductor material is different from the first semiconductor material. An interface of the second semiconductor material with the first semiconductor material has facets. A surface of the second semiconductor material interfacing with the substrate is non-planar.

Semiconductor structures and methods of forming thereof

A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

Integrated circuit fin layout method

Growing community of inventors

Fongshan, Taiwan

Chih-Hsin Ko