Via Technologies, Inc.

Egis Technology Inc.

Chih-Hsien Weng

Cheng-Yuan Wu

Wen-Hsu Huang

Tai-Cheng Chen

Kuo-Ching Chen

Yung-Fu Chen

Chen-Hua Hsi

Jan-Shian Shiao

Chih-Ming Yuan

Teng-Chuan Hsieh

The disclosure provides a fingerprint sensor and a fingerprint sensing method thereof. The fingerprint sensor includes an optical sensing array, an analog front end circuit and an image processing circuit. The optical sensing array is configured for sequentially outputting a plurality of analog fingerprint images corresponding to a finger. The analog front end circuit is coupled to the optical sensing array. The analog front end circuit is configured for sequentially receiving and converting the plurality of analog fingerprint images into a plurality of first digital fingerprint images. The image processing circuit is coupled to the analog front end circuit. The image processing circuit is configured for sequentially superimposing the plurality of first digital fingerprint images to generate an enhanced fingerprint image.

Fingerprint sensor and fingerprint sensing method thereof

A method of managing power consumption of a network interface is provided. The method is capable of cutting off the power and the clock signal supply to the MAC and the PHY receiving terminals of the network interface when the user disables the wake-up function, and when the user enables the wake-up function, the power and the clock signal are supplied to the receiver of the medium access control unit and the receiver of the physical layer unit.

Method of managing power consumption of a network interface

A packet receiving-transmitting method is provided for use on a packet-switching network, such as Ethernet, for the purpose of handling packets more efficiently than the prior art. By this method, each received packet is stored in a packet buffer of a fixed size and associated with just one descriptor. Based on a threshold logical segmentation size determined by the network protocol, each packet buffer is partitioned into a plurality of segments, each having an ending point linked to an Early Receive/Transmit interrupt signal with the ending point of the packet buffer being linked to an OK interrupt signal. In response to each Early Receive/Transmit interrupt signal, the packet data stored are retrieved and forwarded; and in response to the OK interrupt signal, all the remaining packet data in the packet buffer are retrieved and forwarded. After this a write-back operation is performed on the associated descriptor so as to reset the descriptor to unused status. This method can help allow the memory allocation to each received packet to be more efficient. Moreover, it can help reduce the total number of required interrupts during the receiving-transmitting operation for each received packet, and also can help reduce the total number of descriptor write-back operations for each received packet. This method is therefore significantly more advantageous in terms of system performance than the prior art.

Packet receiving method on a network with parallel and multiplexing capability

A method of configuring a computer system capable of being woken up on a LAN A core power is actuated for an interval by performing a Pre-Advanced Configuration and Power Interface (Pre-ACPI) routine. Next, a PCI clock signal is retrieved in the fixed interval and then an Ethernet ID is loaded using the PCI clock signal, so as to set a south bridge to a standby mode capable of receiving a wake-up event. As a result, use of an oscillator in conventional methods can be reduced, and the computer system can be configured to be capable of being woken-up on LAN, without requiring the start-up procedure, so that the computer system may be awoken on the LAN even after an abnormal shutdown.

Method of configuring a computer system capable of being woken up on LAN

A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p&#x2212;q)th detected points but a second level at the (p+1)th detected point.

Method and device for verifying frequency of clock signal

A method and system of testing a chip for testing a circuit module in the chip. The system is integrated into the chip. The reference clock and the test command are sent to the testing system serially. The testing system, in response to the test command, performs test actions on the circuit module, producing a test result. The test result is serially sent to the test machine.

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Taipei, Taiwan

Chih-Hsien Weng