Mosel Vitelic Corporation

Brilliance Semiconductor Inc.

Chih-Hsien Wang

Min-Liang Chen

Thomas Chang

San-Jung Chang

Chih-hsun Chu

Cheng-Tsung Ni

Saysamone Pittikoun

Minn-Horng Juang

Doung-Her Tsai

A refresh-free ultra-low power pseudo dynamic random access memory (DRAM). A clock that controls a DRAM is used to perform 1-bit read, 1-bit write, or a non-read and non-write operation. The clock includes a first read signal, a first write signal, or a first non-read and non-write signal. An interface circuit generates a second read signal, a second write signal, or a second non-read and non-write signal according to the first read signal, the first write signal, or the first non-read and non-write signal, respectively. A static random access memory (SRAM) cell is coupled with the interface circuit for performing the 1-bit read according to the second read signal, the 1-bit write according to the second write signal, or the non-read and non-write operation according to the non-read and non-write signal.

Refresh-free ultra low power pseudo DRAM

A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

Method for forming LDD CMOS using double spacers and large-tilt-angle

A method for fabricating a CMOS integrated circuit device with less masking steps than a conventional device. The present method includes a step of providing a semiconductor substrate with a well region, a gate dielectric layer, and a polysilicon gate electrode. The gate dielectric layer is overlying the well region, and the polysilicon gate electrode is overlying the gate dielectric layer. The present method also includes forming a first thermal oxide thickness overlying the polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions. The first thermal oxide thickness is greater than the second thermal oxide thickness, and both layers are defined during the same step. A mask exposes first LDD regions and first source drain regions. The present method then angle implants a first impurity through the first thermal oxide thickness and the second thermal oxide thickness, and implants a second impurity through the second thermal oxide thickness, thereby forming the completed source/drain region in a single masking step.

Method for forming LDD CMOS

The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate comprising an multiple layer of films (105, 107, 109). These films include an oxide layer (105) overlying the substrate, a polysilicon layer (107) overlying the oxide layer, and a nitride layer (109) overlying the polysilicon layer. The invention also uses a step of removing a first portion of the nitride layer and a first portion of the polysilicon layer defined underlying the first portion of the nitride layer and removing a second portion of the nitride layer and a second portion of the polysilicon layer defined underlying the second portion of the nitride layer. This sequence of steps provides a partially completed semiconductor structure that defines isolation regions before forming well regions for active devices.

Method for manufacturing semiconductor devices using double-charged

The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.

Method of making double-poly MONOS flash EEPROM cell

The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration. The present invention is characterized in that no threshold voltage adjustment implantation to the semiconductor substrate is needed prior to the growth of the gate structure, and in stead, the diffusion ability of the pocket-implanted impurities in the step (c) can concurrently adjust the threshold voltage of the device.

Process for fabricating MOS device having short channel

A method for preventing substrate damage during semiconductor fabrication, comprising, forming a pad oxide layer on the substrate, depositing a polysilicon buffer layer on the pad oxide layer, ion-implanting fluorine into the polysilicon buffer layer, depositing a silicon nitride layer on the polysilicon buffer layer, defining an active region in the substrate, forming a local oxide layer beside the surface of the active region, removing the silicon nitride layer, removing the polysilicon buffer layer by dry etching, and etching the pad oxide layer to expose the substrate surface of active region.

Method for preventing substrate damage during semiconductor fabrication

A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.

Method of making EEPROM cell device with polyspacer floating gate

The present invention discloses a double poly metal oxide.backslash.nitride.backslash.oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.

Double-poly monos flash EEPROM cell

A method and resulting integrated circuit device, and in particular a CMOS integrated circuit device, having a fabrication method and structure therefor for an improved lightly doped drain region. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectic over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 45.degree. or greater from a perpendicular to the gate electrodes in both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well region. Sidewall spacers are then formed on edges of the gate electrodes. The method then performs two separate N type implants into the P type well region, each at different angles and dosages to form the N type LDD source/drain region for an NMOS device. The method also performs two separate P type implants into the N type well region, each at different angles and dosages to form the P type LDD source/drain region for a PMOS device. The present LDD fabrication method provides a relatively consistent and easy to fabricate CMOS LDD region, with less masking steps and improved device performance.

Process for forming LDD CMOS using large-tilt-angle ion implantation

A method and structure therefor for the formation of lightly doped drain regions, typically used in the manufacture of a field effect devices. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 20 degrees and greater from a perpendicular to the gate electrodes into both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well, and a buried region in the N type well. Sidewall spacers are then formed on edges of the gate electrodes. An N type implant step is then performed on the P type well region to form the source/drain region of a NMOS device. The method then performs two separate P type implants into the N type well, each at different angles and dosages, to form the P type LDD source/drain region for a PMOS device. The PMOS device includes the buried region which acts as a punchthrough stop, typically used to decrease short channel effects.

Growing community of inventors

Hsinchu, Taiwan

Chih-Hsien Wang