Taiwan Semiconductor Manufacturing Comp. Ltd.

Dell Products Inc.

Quanta Computer Incorporated

Institute of Nuclear Energy Research

Other

Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan

Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.o.c

Microtek International Inc.

Institute of Nuclear Energy Research, Atomic Energy Council

Axcen Photonics Corp.

Tty Biopharm Company, Limited

Chih-Hsien Chang

Ruey-Bin Sheen

Tsung-Hsien Tsai

Cheng-Hsiang Hsieh

Mao-Hsuan Chou

Ya-Tin Chang

Min-Shueh Yuan

Chin-Ming Fu

Tsung-Che Lu

Yung-Chow Peng

Ying-Yu Hsu

Chao Chieh Li

Chen-Ting Ko

Ting-Kuei Kuan

Robert Bogdan Staszewski

Ming Hsien Tsai

Chia-Chun Liao

Yu-Tso Lin

Hsiang-Yin Hung

Te-Wei Lee

Seyednaser Pourmousavian

Matt Li

Wen-Shen Chou

Chih-Wei Hung

Po-Zeng Kang

Ming-Hsin Li

Yi-Chang Chen

Su-Jung Chen

Hsien-Ming Tsai

Shu-Pei Chiu

Wen-Tzung Chen

Fu-Lung Hsueh

Chung-Hui Chen

Tung-Tsun Chen

Shyh-An Chi

Tsung-Hsin Yu

Tien-Chien Huang

Jinn-Yeh Chien

Raymond Dewine Heistand, Ii

Chao-Chieh Li

Chih-Kuang Wang

Chun-Chieh Chang

Chun-Te Lee

Chien-Chun Tsai

Shih-Ying Lee

Chun-Ying Huang

Shih-Hung Lan

Sheng-Nan Lo

Ying-Kai Fu

Shyh-Yi Chyi

Chun-Yang Tseng

Ming-Wei Chen

Shiang-Rong Chang

Chun-Fang Feng

Renjeng Chiang

Ching-Hui Kuo

Weichih Chen

Te-Wei Li

Chung-Yen Li

Chen-Hsiang Hsieh

Yuan-Ruei Huang

Te-Ming Liao

Jheng-Tong Wu

Bao-Jen Pong

Cheng-Ta Chen

Chien-Cheng Yang

Charng-Feng Kao

Wei-Chuan Hsu

Kuo-Hsien Fan

Yin-Mao Hsu

Ruey-Bin Shen

Kwo-Ping Chang

Te-Jung Chen

Ming-Shiuan Wu

Chin-Yang Wu

Chang-An Chen

Chu-Nian Cheng

Ming-Syuan Lin

An-Jim Long

A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.

Sense amplifier and method thereof

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

Circuit, chip and semiconductor device

A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

Circuits designed and manufactured with first and second fin boundaries

Method and apparatus for optimizing circuit design are disclosed. In one aspect, the method includes receiving a circuit design of an integrated circuit and identifying a first circuit design of a first subsystem of the IC and a second circuit design of a second subsystem of the IC. The first subsystem operates on a plurality of digital variable signals and the second subsystem operates on a plurality of analog variable signals. The method also includes synthesizing a first HDL netlist based on the first circuit design, synthesizing a second HDL netlist based on the second circuit design, and obtaining behaviors of the circuit design of the IC using a single HDL-based simulator with both the first HDL netlist and the second HDL netlist as inputs.

Apparatus and method of optimizing an integrated circuit design

A sensing circuit coupled to a sensor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an oscillator. The first transistor, coupled to a first current source and the sensor, receives a sensing current from the sensor. A gate terminal of the first transistor is connected to a source terminal of the first transistor. The second transistor, coupled to the first transistor and a second current source, generates a first current according to the sensing current. The first current is greater than the sensing current. The third transistor, coupled to the second transistor and the second current source, generates a second current according to the first current. The fourth transistor, coupled to the third transistor, generates a third current. The oscillator is coupled to the fourth transistor. The oscillator generates a signal having an oscillation frequency according to the third current.

Sensing circuit and sensing method thereof

A circuit and a method for adjusting a periodic input signal are provided. The circuit includes a duty cycle calibration (DCC) device, a phase adjusting device, and a duty cycle measurement (DCM) device. The DCC device is configured to generate a first signal and a second signal in response to the periodic input signal. The first signal and the second signal have different phases. The phase adjusting device is configured to receive the first signal and the second signal to generate a third signal by combining the first signal and the second signal based on a selection signal. The DCM device is configured to measure and adjust a duty cycle of the third signal so that the selection signal is adjusted to generate a periodic output signal. A frequency of the periodic output signal is twice that of the periodic input signal.

Circuit and method for duty cycle adjustment

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Systems and methods for phase locked loop realignment with skew cancellation

An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.

Impedance measurement circuit and impedance measurement method thereof

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

System and semiconductor device therein

Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Programmable regulator voltage controlled ring oscillator

The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is β times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.

System and method of measuring capacitance of device-under-test

An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

System for signal propagation and method of operating the same

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Loop gain auto calibration using loop gain detector

Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

Systems and methods for duty cycle measurement

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Delay lock loop circuits and methods for operating same

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Taipei, Taiwan

Chih-Hsien Chang