Mediatek Corporation

Industrial Technology Research Institute

Chih-Hong Lou

Hung-I Chen

Chi-Yun Wang

Yen-Chuan Huang

Jen-Huan Tsai

Li-Han Hung

Min-Hua Wu

Chi Yun Wang

Chih-Yuan Hsu

Chao-Hsin Lu

Tzu-Yi Yang

Kuan-Hung Chen

Kuan-Chun Chen

Chih-Jung Chen

Chun-Ming Hsu

Po-Min Wang

Wei-Yang Ou

Yi-Jhan Sie

Chia-Chun Liu

Yen-Jen Liu

Po-Jung Chang

Yan-Jiun Chen

Tzu-Hsuin Peng

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

System improving signal handling

A low-dropout regulator (LDO) capable of providing high power-supply rejection ratio (PSRR) and good reverse isolation. The LDO may include a core circuitry and a reverse isolation circuitry. The core circuitry may include a PSRR circuitry coupled to an output node and configured to provide high PSRR at the output node. The reverse isolation circuitry may be configured to provide good reverse isolation at the output node by, for example, providing current in response to ripples at the output node. The reverse isolation circuitry may be configured with bandwidth higher than that of the core circuitry such that it can provide fast transient response. The reverse isolation circuitry may be configurable and/or reconfigurable for a desirable reverse isolation performance. The reverse isolation circuitry may be configurable and/or reconfigurable to trade off between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

Reconfigurable series-shunt LDO

A voltage regulator apparatus includes operational amplifier, first resistor, second resistor, driving transistor, amplifier circuit, and output circuit. The operational amplifier has first input terminal coupled to reference voltage, second input terminal, and output terminal. The first resistor has first terminal coupled to second input terminal. The second resistor is coupled between first resistor and ground level. The driving transistor has control terminal coupled to output terminal of operational amplifier and first terminal coupled to second terminal of first resistor. The amplifier circuit is coupled to output terminal of operational amplifier and configured to sense output voltage of voltage regulator apparatus to amplify the sensed voltage with specific gain to regulate a transistor of output circuit. The transistor has control terminal controlled by amplifier circuit. The output voltage is generated at first terminal of the transistor.

Voltage regulator apparatus offering low dropout and high power supply rejection

An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

Analog-to-digital converter with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay compensation

A PLL includes a phase frequency detector (PFD), a charge pump, a capacitor coupled to the charge pump, an analog-to-digital convertor (ADC), a noise canceller, an accumulator, a loop filter, an oscillator, a digital block and a frequency divider. The PFD detects a phase difference between a reference signal and a divided signal. The charge pump generates a charge pump signal in response to the phase difference. The ADC converts the charge pump signal to a first digital signal, and quantizes it to a second digital signal. The noise canceller forms a shaped noise signal according to the first and second digital signals, and eliminates the shaped noise signal at the output of the noise canceller to generate a noise cancelled signal. The accumulator accumulates the noise cancelled signal. The loop filter filters the accumulated signal. The oscillator provides an output oscillating signal in response to the filtered signal.

Phase lock loop

A current controlling device includes: a first resistive circuit arranged to selectively conduct a first current to a first output terminal from a first input terminal; and a second resistive circuit arranged to selectively conduct a second current to a second output terminal from the first input terminal; wherein when the first resistive circuit conducts the first current to the first output terminal and when the second resistive circuit does not conduct the second current to the second output terminal, the first input terminal has a first input impedance; when the first resistive circuit does not conduct the first current to the first output terminal and when the second resistive circuit conducts the second current to the second output terminal, the first input terminal has a second input impedance substantially equal to the first input impedance.

Current controlling device and signal converting apparatus applying the current controlling device

A resonating device includes: an amplifying circuit having a first input terminal, and an output terminal for outputting an output signal; a first feedback circuit coupled between the first input terminal and the output terminal of the amplifying circuit; a second feedback circuit, coupled between the first input terminal and the output terminal of the amplifying circuit; and a gain adjusting circuit, having an input terminal for receiving an input signal, and a first output terminal coupled to the first input terminal of the amplifying circuit; wherein a first equivalent impedance on a first intermediate terminal in the first feedback circuit substantially equals a second equivalent impedance on a second intermediate terminal in the second feedback circuit, and the gain adjusting circuit is arranged to tune a transfer function from the input signal to the output signal.

Resonating device with single operational amplifier

A signal modulating device includes: an integrating circuit arranged to generate an integrated signal according to a scaled analog signal and a first feedback signal; a resonating circuit arranged to generate a resonating signal according to the integrated signal; a first signal converting circuit arranged to convert the resonating signal into a digital output signal; a second signal converting circuit arranged to convert the digital output signal into the first feedback signal; and a first impedance circuit having a first terminal receiving an analog signal and a second terminal coupled to the resonating circuit for altering the location of zeros in the forward-path transfer function and consequently shaping the signal transfer function (STF) of the signal modulating device; and a second impedance circuit having a first terminal receiving the analog signal and a second terminal coupled to the integrating circuit for generating the scaled analog signal.

Signal modulating device capable of reducing peaking in signal transfer function

A low pass filter includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential operational amplifier, wherein the first amplifier stage is arranged to process a differential input signal to generate a differential intermediate signal, the differential input signal having a first input signal and a second input signal, and the differential intermediate signal having a first intermediate signal and a second intermediate signal. The second amplifier stage has no common-mode feedback and is arranged to process the differential intermediate signal to generate a differential output signal, wherein the differential output signal has a first output signal corresponding to the first input signal and a second output signal corresponding to the second input signal. Since the noisy common-mode feedback is removed from the second amplifier stage, the overall common-mode noise of the low pass filter can be decreased.

Low pass filter with common-mode noise reduction

A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.

Multi-mode OPAMP-based circuit

An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal.

Analog-to-digital converting device and analog-to-digital converting method

A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.

Dynamic feed-forward OPAMP-based circuit

A microphone bias circuit is disclosed. A current source provides a first current. A voltage buffer provides a first reference voltage. A microphone coupled between the current source and the first reference voltage receives acoustic waves and converts the received acoustic waves to a second current. A loading device coupled between the current source and a second reference voltage lower than the first reference voltage outputs an output voltage according to the first current and the second current.

Microphone bias circuits

A digital-to-analog converter includes an operational amplifying circuit, a switched capacitor circuit, an R-string sub-circuit, and a direct-charge transfer circuit. The operational amplifying circuit has a pair of differential input ends and a pair of differential output ends. The switched capacitor circuit is coupled to the pair of differential input ends of the operational amplifying circuit. The R-string sub-circuit is coupled to the switched capacitor circuit and the pair of differential input ends of the operational amplifying circuit. The direct-charge transfer circuit is coupled to the pair of differential input ends and the pair of differential output ends of the operational amplifying circuit.

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Yilan County, Taiwan

Chih-Hong Lou