S3 Graphics Co., Ltd.

Chih-Hong Fu

Zhou Hong

I-Chung Ling

Huai-Shih Hsu

Dong-Ying Kuo

Randy X Zhao

Roger Niu

A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available slots of the cache are allocated to the texture maps. Sometimes, more slots are allocated to the largest texture map. At other times, more slots are allocated to the texture map which is likely to be used most often. The slots can also be allocated equally to all of the texture maps needed.

Dynamic allocation of texture cache memory

A synchronized two-level cache including a level 1 cache and a level 2 cache is implemented in a graphics processing system. The level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of a synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.

Synchronized two-level graphics processing cache

A synchronized two-level cache including a Level 1 cache and a Level 2 cache is implemented in a graphics processing system. The Level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.

A command parser,is coupled to an incoming data stream to insert an end of state token at the end of a group of state data,and an end of primitive token at the end of a group of primitive data,to create a parsed data stream. The parsed state data stream is transmitted to a state controller,which loads state data,into shadow stages,The state controller,validates a shadow stage,upon receiving an end of state group token. The parsed primitive data,are also transmitted to primitive controllers,The primitive controllers,prevent primitive data from being transmitted into a processing element,responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller,ascertains whether the first shadow stage,has been validated. If it has, the primitive controller,loads the state data,into the working stage,and allows the primitive data,to be transmitted to the processing element,where it is processed in accordance with the state data,in the working stage,In an alternate embodiment, a dirty bit,is used to indicate that the state data,received by the state controller,is identical to previously received state data,The primitive controller,ascertains whether the dirty bit,of the first shadow stage,associated with its processing element,is marked. If the dirty bit,is unmarked, the primitive controller,allows the primitive data,to be processed by the processing element,without delay in accordance with the existing state information in the working registers.

Growing community of inventors

Sunnyvale, CA, United States of America

Chih-Hong Fu