Macronix International Co., Ltd.

Macroniz Interntaional Co., Ltd.

Chih-He Chiang

Chung-Kuang Chen

Han-Sung Chen

Yi-Ching Liu

Shang-Chi Yang

Yi-Ting Lai

Che-Wei Liang

Chung-Han Wu

A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

Memory device, failure bits detector and failure bits detection method thereof

A pre-match method includes: receiving an initial address; gradually increasing a current address according to the initial address; adding an offset value to the current address for generating a match address; generating a hit parameter by comparing the match address with at least one defect address stored in the mapping table; generating a redundancy address corresponding to the match address; and setting a Y-direction address as either the redundancy address or the current address according to the hit parameter.

Pre-match system and pre-match method

A memory device includes a memory array including a number of memory cell strings, a number of bit lines, a number of pre-charge circuits coupled to the memory cell strings, and a number of sense amplifier circuits coupled to the memory cell strings through the bit lines. Each memory cell string includes at least one first select transistor, a second select transistor and at least one memory cell. Each bit line includes a third select transistor, and is coupled to a memory cell string. During a pre-charging stage, the pre-charge circuits provide a first voltage to pre-charge the memory cell strings. During a programming stage, for the memory cell strings to be inhibited, the sense amplifier circuits provide a second voltage lower than the first voltage. For the memory cell strings to be programmed, the sense amplifier circuits provide a third voltage lower than the second voltage.

Memory device and operation method thereof

A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read.

Memory array

A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. A method of operating the memory array is also shown, including, in reading a selected memory cell, applying voltages to the gate, the drain and the source thereof respectively from a word line, a first global bit line and a neighboring second global bit line, and turning on a select transistor coupled to a third global bit line separate from the first and the second ones by at least one other global bit line.

Growing community of inventors

Zhubei, Taiwan

Chih-He Chiang