Himax Technologies, Inc.

Himax Media Solutions, Inc.

Ncku Research and Development Foundation

Himas Media Solutions, Inc.

Himax Media Solution, Inc.

Chih-Haur Huang

Soon-Jyh Chang

Jin-Fu Lin

Kuo-Chan Huang

Chung-Ming Huang

Chun-Cheng Liu

Guan-Ying Huang

Yuan-Kai Chu

Mu-Hsien Hsu

An-Sheng Chao

Shih-Ming Luo

Huei-Fang Shiau

A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.

Source driver output stage circuit, buffer circuit and voltage adjusting method thereof

An audio amplifier includes a timing control circuit, an amplifying circuit, and a bias control circuit. The timing control circuit generates a first power down signal and a second power down signal, in which the first power down signal is asserted before the second power down signal is asserted. The amplifying circuit receives a bias voltage to amplify an audio signal and is deactivated when the first power down signal is asserted. The bias control circuit provides the bias voltage for the amplifying circuit and is deactivated when the second power down signal is asserted.

Method of powering down an audio amplifier with timing circuit to power down bias control and amplifying circuits in sequence

A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

Successive approximation register ADC with a window predictive function

The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

Method and apparatus of controlling an operational status of an electronic device

Audio amplifier with timing circuit to power down bias control and amplifying circuits in sequence

A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

Sample hold circuit and method for sampling and holding signal

An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.

Analog-to-digital conversion unit and analog-to-digital converting method thereof

A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage.

Sample hold circuit and method thereof for eliminating offset voltage of analog signal

The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.

Device for jitter measurement and method thereof

An analog-to-digital conversion circuit is provided. A voltage divider of the analog-to-digital conversion circuit regulates a voltage range received by a sample holder of analog-to-digital conversion circuit. Accordingly, a first half of the sample holder can use an electrical device with a low operating voltage. Since an operation speed of the electrical device with the low voltage is faster than an electrical device with a high operating voltage, an operation frequency of the sample holder can be raised.

Analog-to-digital conversion circuit

An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Stage-resolution scalable opamp-sharing technique for pipelined/cyclic ADC

A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data.

Receiver system and method for automatic skew-tuning

An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage, and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds the dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage.

Analog to digital converter having digital correction logic that utilizes a dither signal to correct a digital code

A method for enhancing resolution of digital signals converted from analog signals is provided. An analog input signal is converted into N-bit digital outputs, where N is a positive integer. The N-bit digital outputs are interpolated to add one or more least significant bit orders for the N-bit digital outputs. One or more dither values are generated as least significant bits corresponding to the least significant bit orders and the dither values are superimposed on the interpolation of the N-bit digital outputs. An A/D converter is also provided herein.

A/D converter and method for enhancing resolution of digital signal

An analog-to-digital converter includes a sample-and-hold amplifier (SHA), a plurality of stages of analog-to-digital converting (ADC) units and an adjustment circuit. The SHA samples an analog input signal. The ADC units serially converts the analog input signal sampled by the SHA into corresponding digital values, in which a first stage of the ADC units generates the digital value including most significant bits. The adjustment circuit controls the SHA by checking the most significant bits from the first stage of the ADC units to modify offsets of the analog input signal with respect to a reference value. A method for adjusting an analog input signal in an analog-to-digital converter and a method for converting an analog input signal into a digital signal are also disclosed herein.

Growing community of inventors

Tainan County, Taiwan

Chih-Haur Huang