Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Chih-Hao Yu

Cheng-Hsien Chou

Chien-Ting Lin

Che-Hua Hsu

Li-Wei Cheng

Tian-Fu Chiang

Chien-Ming Lai

Yi-Wen Chen

Guang-Hwa Ma

Chia-Pin Lin

Chang-Yun Chang

Sai-Hooi Yeong

Sheng-Chen Wang

Chih-Hao Chang

Hung-Ming Chen

Hsiu-Hao Tsao

Bone-Fong Wu

Chang-Jhih Syu

Jung-Tsung Tseng

Yu-Jiun Peng

Wei-Yang Lee

Ming-Feng Shieh

Kuo-Feng Yu

Shao-Ming Yu

Yen-Ting Chen

Wei-Yuan Lu

Jian-Hao Chen

Shu-Han Chen

Wei-Jen Lai

Jin-Mu Yin

Chun-Hsien Lin

Chin-Fu Lin

Nien-Ting Ho

Yu-jiun Peng

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Structure having gate spacers with projecting portions extending into a gate dielectric

A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

Gate formation of semiconductor devices

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

Multi-gate semiconductor device with inner spacer and fabrication method thereof

A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

Inner spacer features for multi-gate transistors

The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

Inner spacer liner

A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

Lightly-doped channel extensions

A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.

Methods for manufacturing a transistor gate by non-directional implantation of impurities in a gate spacer

A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure. The second fin structure includes a first layer including a first semiconductor material. The second fin structure further includes a second layer including a second semiconductor material disposed over the first layer. The second layer has a vertical sidewall. The second semiconductor material is different from the first semiconductor material. A gate structure is disposed over the semiconductor substrate and wraps around the first and second layers of the second fin structure.

Structure and method for FINFET device

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Tainan, Taiwan

Chih-Hao Yu