Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Au Optronics Corporation

Taiwan Semiconductor Manufacturing Co., Ltd.

Parabellum Strategic Opportunities Fund LLC

Pixart Imaging Incorporated

Realtek Semiconductor Inc.

Coretronic Corporation

Wistron Neweb Corporation

Macronix International, Col, Ltd.

Chih-Hao Wang

Kuo-Cheng Chiang

Kuan-Lun Cheng

Kuo-Cheng Ching

Chia-Hao Chang

Ching-Wei Tsai

Cheng-Chi Chuang

Shi Ning Ju

Lin-Yu Huang

Yu-Ming Lin

Huan-Chieh Su

Li-Zhen Yu

Jia-Chuan You

Kuan-Ting Pan

Jia-Ni Yu

Zhi-Chang Lin

Carlos H Diaz

Shi-Ning Ju

Chun-Hsiung Lin

Chung-Wei Hsu

Lung-Kun Chu

Wai-Yi Lien

Mao-Lin Huang

Shih-Cheng Chen

Chun-Yuan Chen

Jung-Hung Chang

Tien-Lu Lin

Pei-Hsun Wang

Ying-Keung Leung

Sheng-Tsung Wang

Sai-Hooi Yeong

Guan-Lin Chen

Zhiqiang Wu

Lo-Heng Chang

Chih-Chao Chou

Jui-Chien Huang

Wei-Hao Wu

Jean-Pierre Colinge

Yi-Ruei Jhan

Kuan-lun Cheng

Pei-Yu Wang

Chung-Cheng Wu

Yi-Hsun Chiu

Shang-Wen Chang

Bo-Feng Young

Min Cao

Chi-Wen Liu

Yu-Xuan Huang

Chih-Yu Chang

Gwan Sin Chang

Ta-Pen Guo

Kai-Chieh Yang

Wen-Hsing Hsieh

Yi-Hsiung Lin

Jhon Jhy Liaw

Yen-Ming Chen

Chenming Hu

Hou-Yu Chen

Chi-On Chui

Yee-Chia Yeo

Yen-Ping Wang

Teng-Chun Tsai

Chih-Liang Chen

Pang-Yen Tsai

Tai-I Yang

Kai-Hsuan Lee

Tzer-Min Shen

Yi-Bo Liao

Chi On Chui

Keng-Chu Lin

Cheng-Ting Chung

Yi-Ming Sheu

Wei-Yang Lee

Ling-Yen Yeh

Chih-Hung Chen

Wei-Sheng Yun

Yeur-Luen Tu

Chung-Yi Yu

Cheng-Ta Wu

Wen-Chin Lee

Chun-Chieh Lin

Liang-Gi Yao

Ken-Ichi Goto

Chih-Ming Sun

Chia-Wei Su

Bo-Yu Lai

Huicheng Chang

Chung-Liang Cheng

Hun-Jan Tao

Sung-Li Wang

Li-Ting Wang

Wei-Jung Lin

Cheng-Tung Lin

Chun-Yen Chang

Hung-Chang Sun

Min-Hwa Chi

Yi-Hsuan Hsiao

Shih-Ting Hung

Kuo-Yin Lin

An integrated circuit (IC) structure includes a first channel region, a first gate metal engaging the first channel region, a first dielectric material layer disposed under the first gate metal and on an end of the first gate metal, a second channel region, a second gate metal engaging the second channel region, a second dielectric material layer disposed under the second gate metal and on an end of the second gate metal, and a dielectric block disposed between the end of the first gate metal and the end of the second gate metal. A horizontal portion of the first dielectric material layer abuts a horizontal portion of the second dielectric material layer, and the horizontal portion of the first dielectric material layer and the horizontal portion of the second dielectric material layer are in physical contact with the dielectric block.

Fill fins for semiconductor devices

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

Gate-all-around structure and methods of forming the same

An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The integrated circuit includes a backside trench through the substrate that removes a lowest semiconductor nanosheet of the first nanosheet transistor while leaving the lowest semiconductor nanosheet of the second nanosheet transistor. The backside trench is filled with a dielectric material.

Integrated circuit with backside trench for nanosheet removal

A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and a conductive feature disposed in the ILD layer and electrically coupled to the first epitaxial S/D feature and the second epitaxial S/D feature. The conductive feature includes first portions having bottom surfaces contacting the first and the second epitaxial S/D features, and a second portion having a bottom surface contacting the ILD layer. The bottom surface of the second portion is above the bottom surface of the first portions.

Methods of forming source/drain contacts in field-effect transistors

Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.

Gate contact structure

The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

Power reduction in finFET structures

A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.

Replacement material for backside gate cut feature

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.

Semiconductor device structure and methods of forming the same

Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration.

Semiconductor devices and methods of fabrication thereof

A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.

Field effect transistor with source/drain via and method

A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

Multi-layer channel structures and methods of fabricating the same in field-effect transistors

A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a front-side interconnection structure, and a backside via. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the gate structure and are connected to the channel layer. The front-side interconnection structure is on a front-side of the first source/drain epitaxial structure. The backside via is connected to a backside of the first source/drain epitaxial structure. A backside surface of the first source/drain epitaxial structure is at a height between a height of a backside surface of the backside via and a height of a backside surface of the gate structure.

Semiconductor device and manufacturing method thereof

A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Gate isolation structure

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

Method for forming semiconductor device

Growing community of inventors

Hsinchu County, Taiwan

Chih-Hao Wang