Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Au Optronics Corporation

Pixart Imaging Incorporated

Parabellum Strategic Opportunities Fund LLC

Realtek Semiconductor Inc.

Coretronic Corporation

Wistron Neweb Corporation

Macronix International, Col, Ltd.

Chih-Hao Wang

Kuo-Cheng Chiang

Kuan-Lun Cheng

Kuo-Cheng Ching

Chia-Hao Chang

Ching-Wei Tsai

Cheng-Chi Chuang

Shi Ning Ju

Yu-Ming Lin

Lin-Yu Huang

Huan-Chieh Su

Li-Zhen Yu

Jia-Chuan You

Kuan-Ting Pan

Carlos H Diaz

Jia-Ni Yu

Shi-Ning Ju

Zhi-Chang Lin

Chun-Hsiung Lin

Chung-Wei Hsu

Wai-Yi Lien

Lung-Kun Chu

Mao-Lin Huang

Shih-Cheng Chen

Chun-Yuan Chen

Tien-Lu Lin

Ying-Keung Leung

Jung-Hung Chang

Pei-Hsun Wang

Sai-Hooi Yeong

Sheng-Tsung Wang

Zhiqiang Wu

Jui-Chien Huang

Chih-Chao Chou

Wei-Hao Wu

Lo-Heng Chang

Guan-Lin Chen

Jean-Pierre Colinge

Yi-Ruei Jhan

Kuan-lun Cheng

Pei-Yu Wang

Chung-Cheng Wu

Yi-Hsun Chiu

Bo-Feng Young

Shang-Wen Chang

Min Cao

Chi-Wen Liu

Yu-Xuan Huang

Chih-Yu Chang

Gwan Sin Chang

Ta-Pen Guo

Kai-Chieh Yang

Wen-Hsing Hsieh

Yi-Hsiung Lin

Ting-Hung Hsu

Jhon Jhy Liaw

Yen-Ming Chen

Chenming Hu

Hou-Yu Chen

Chi-On Chui

Yee-Chia Yeo

Yen-Ping Wang

Teng-Chun Tsai

Chih-Liang Chen

Pang-Yen Tsai

Tai-I Yang

Kai-Hsuan Lee

Tzer-Min Shen

Yi-Bo Liao

Chi On Chui

Keng-Chu Lin

Yi-Ming Sheu

Wei-Yang Lee

Ling-Yen Yeh

Chih-Hung Chen

Cheng-Ting Chung

Wei-Sheng Yun

Jin Cai

Yeur-Luen Tu

Chung-Yi Yu

Cheng-Ta Wu

Wen-Chin Lee

Chun-Chieh Lin

Liang-Gi Yao

Ken-Ichi Goto

Chih-Ming Sun

Chia-Wei Su

Bo-Yu Lai

Huicheng Chang

Hun-Jan Tao

Sung-Li Wang

Li-Ting Wang

Cheng-Tung Lin

Wei-Jung Lin

Chun-Yen Chang

Hung-Chang Sun

Min-Hwa Chi

Shih-Ting Hung

Kuo-Yin Lin

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Integrated circuits with finFET gate structures

Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Integrated circuits with gate cut features

The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Semiconductor structure and method of fabricating the semiconductor structure

A method includes forming a first semiconductor layer over a substrate; forming a dummy material covering a first sidewall of the first semiconductor layer; forming source/drain epitaxy structures over the substrate and in contact with the first semiconductor layer; forming an interfacial layer on a top surface and a second sidewall of the first semiconductor layer that are uncovered by the dummy material; removing the dummy material to expose the first sidewall of the first semiconductor layer; forming a second semiconductor layer on the first sidewall of the first semiconductor layer after removing the dummy material, in which the second semiconductor layer and the source/drain epitaxy structures have different conductivity types; and forming a gate electrode over the interfacial layer.

Semiconductor device and method for forming the same

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Semiconductor device structure and methods of forming the same

According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Uniform gate width for nanostructure devices

The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

FET with wrap-around silicide and fabrication methods thereof

A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Multi-gate device and related methods

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

FinFET structure with airgap and method of forming the same

A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. A left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. The semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. A left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. In addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.

Nanostructure with various widths

A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

Semiconductor devices with backside power rail and backside self-aligned via

A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Source/drain metal contact and formation thereof

A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

Integrated circuit structure with backside interconnection structure having air gap

A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.

Semiconductor device with metal cap on gate

A device according to the present disclosure includes a fin structure disposed on a substrate and including a stack of semiconductor layers that are separated from each other, a dielectric fin disposed on the substrate, a spacer layer disposed on a sidewall of the dielectric fin and extending below the dielectric fin such that the spacer layer prevents the dielectric fin from interfacing with the substrate, an interfacial layer wrapping around each semiconductor layer of the stack, a gate dielectric layer disposed on the interfacial layer wrapping around each semiconductor layer of the stack, and a gate electrode layer including a first portion wrapping around the gate dielectric layer disposed on the interfacial layer and a second portion extending along the spacer layer disposed on the dielectric fin. An airgap extends between the first portion of the gate electrode layer and the second portion of the gate electrode layer.

Device having a gate electrode wrapping around semiconductor layers and proximate to a dielectric fin

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Hsinchu County, Taiwan

Chih-Hao Wang