Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Au Optronics Corporation

Pixart Imaging Incorporated

Parabellum Strategic Opportunities Fund LLC

Realtek Semiconductor Inc.

Coretronic Corporation

Wistron Neweb Corporation

Macronix International, Col, Ltd.

Chih-Hao Wang

Kuo-Cheng Chiang

Kuan-Lun Cheng

Kuo-Cheng Ching

Chia-Hao Chang

Ching-Wei Tsai

Cheng-Chi Chuang

Shi Ning Ju

Yu-Ming Lin

Lin-Yu Huang

Li-Zhen Yu

Huan-Chieh Su

Jia-Chuan You

Kuan-Ting Pan

Jia-Ni Yu

Carlos H Diaz

Zhi-Chang Lin

Shi-Ning Ju

Chun-Hsiung Lin

Chung-Wei Hsu

Lung-Kun Chu

Wai-Yi Lien

Mao-Lin Huang

Shih-Cheng Chen

Chun-Yuan Chen

Jung-Hung Chang

Tien-Lu Lin

Ying-Keung Leung

Pei-Hsun Wang

Sai-Hooi Yeong

Sheng-Tsung Wang

Zhiqiang Wu

Jui-Chien Huang

Chih-Chao Chou

Guan-Lin Chen

Wei-Hao Wu

Lo-Heng Chang

Jean-Pierre Colinge

Yi-Ruei Jhan

Kuan-lun Cheng

Pei-Yu Wang

Chung-Cheng Wu

Yi-Hsun Chiu

Bo-Feng Young

Shang-Wen Chang

Min Cao

Chi-Wen Liu

Yu-Xuan Huang

Chih-Yu Chang

Gwan Sin Chang

Ta-Pen Guo

Kai-Chieh Yang

Wen-Hsing Hsieh

Yi-Hsiung Lin

Jhon Jhy Liaw

Yen-Ming Chen

Chenming Hu

Hou-Yu Chen

Chi-On Chui

Yee-Chia Yeo

Yen-Ping Wang

Teng-Chun Tsai

Chih-Liang Chen

Pang-Yen Tsai

Tai-I Yang

Kai-Hsuan Lee

Tzer-Min Shen

Yi-Bo Liao

Chi On Chui

Keng-Chu Lin

Yi-Ming Sheu

Wei-Yang Lee

Ling-Yen Yeh

Chih-Hung Chen

Cheng-Ting Chung

Wei-Sheng Yun

Jin Cai

Yeur-Luen Tu

Chung-Yi Yu

Cheng-Ta Wu

Wen-Chin Lee

Chun-Chieh Lin

Liang-Gi Yao

Ken-Ichi Goto

Chih-Ming Sun

Chia-Wei Su

Bo-Yu Lai

Huicheng Chang

Hun-Jan Tao

Sung-Li Wang

Li-Ting Wang

Cheng-Tung Lin

Wei-Jung Lin

Chun-Yen Chang

Hung-Chang Sun

Min-Hwa Chi

Yi-Hsuan Hsiao

Shih-Ting Hung

Kuo-Yin Lin

A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Gate isolation structure

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

Method for forming semiconductor device

The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.

Semiconductor structure with self-aligned backside power rail

A method of manufacturing a semiconductor device structure includes bonding a device substrate to a first de-bond layer. The first de-bond layer is disposed on a first carrier substrate, and the device substrate has a first side facing the first carrier substrate and a second side opposite from the first side. The device substrate has a first width. A front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process are performed on the device substrate. A second carrier substrate having a second de-bond layer is bonded on the second side of the device substrate. The first carrier substrate is removed by removing the first de-bond layer. A width of the device substrate remains the first width after removing the first carrier substrate.

Trim free wafer bonding methods and devices

A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.

Semiconductor transistor device structure including nanostructure and gate structure with protection layer and fill layer and method for forming the same

A semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. The shallow trench isolation structure is disposed over the substrate. The epitaxial structures are disposed over the shallow trench isolation structure. The one or more semiconductor channel layers connect the two epitaxial structures. The gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. The gate spacer is in contact with a sidewall of the gate metal layer. From a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.

Semiconductor device and manufacturing method thereof

FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Fin-like field effect transistor patterning methods for achieving Fin width uniformity

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Low parasitic capacitance contact structure

A method of forming a semiconductor device includes etching trenches in a substrate to form semiconductor fins, filling a first one of the trenches with a dielectric fin, forming an insulation material in a second one of the trenches, performing a first recessing process to recess the insulation material and form a gap on a top of the dielectric fin, filling the gap with a dielectric cap, and forming a gate stack across the semiconductor fins and the dielectric fin.

Semiconductor device and formation method thereof

A structure includes a first dielectric feature extending along a first direction, the first dielectric feature having a first side and a second side opposing the first side. The structure includes a first semiconductor layer disposed adjacent the first side of the first dielectric feature, the first semiconductor layer extending along a second direction perpendicular to the first direction. The structure includes a CESL in contact with the first dielectric feature and a portion of the first semiconductor layer, an ILD layer in contact with the CESL and a portion of the first semiconductor layer. The structure further includes a second dielectric feature extending along the first direction, the second dielectric feature including a first dielectric layer in contact with the CESL and a portion of the first semiconductor layer, and a second dielectric layer in contact with the first dielectric layer and a portion of the first semiconductor layer.

Semiconductor device structure including forksheet transistors and methods of forming the same

A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

Semiconductor device with air gaps and method of fabrication thereof

Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Integrated circuits with finFET gate structures

Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Integrated circuits with gate cut features

Growing community of inventors

Hsinchu County, Taiwan

Chih-Hao Wang