Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Au Optronics Corporation

Pixart Imaging Incorporated

Parabellum Strategic Opportunities Fund LLC

Realtek Semiconductor Inc.

Coretronic Corporation

Wistron Neweb Corporation

Macronix International, Col, Ltd.

Chih-Hao Wang

Kuo-Cheng Chiang

Kuan-Lun Cheng

Kuo-Cheng Ching

Chia-Hao Chang

Ching-Wei Tsai

Cheng-Chi Chuang

Shi Ning Ju

Yu-Ming Lin

Lin-Yu Huang

Li-Zhen Yu

Huan-Chieh Su

Kuan-Ting Pan

Jia-Chuan You

Carlos H Diaz

Jia-Ni Yu

Shi-Ning Ju

Zhi-Chang Lin

Chun-Hsiung Lin

Chung-Wei Hsu

Wai-Yi Lien

Lung-Kun Chu

Mao-Lin Huang

Chun-Yuan Chen

Shih-Cheng Chen

Ying-Keung Leung

Tien-Lu Lin

Jung-Hung Chang

Pei-Hsun Wang

Sai-Hooi Yeong

Sheng-Tsung Wang

Zhiqiang Wu

Chih-Chao Chou

Wei-Hao Wu

Lo-Heng Chang

Jui-Chien Huang

Jean-Pierre Colinge

Guan-Lin Chen

Yi-Ruei Jhan

Pei-Yu Wang

Chung-Cheng Wu

Kuan-lun Cheng

Yi-Hsun Chiu

Bo-Feng Young

Shang-Wen Chang

Min Cao

Chi-Wen Liu

Chih-Yu Chang

Yu-Xuan Huang

Gwan Sin Chang

Ta-Pen Guo

Kai-Chieh Yang

Wen-Hsing Hsieh

Yi-Hsiung Lin

Ting-Hung Hsu

Jhon Jhy Liaw

Yen-Ming Chen

Chenming Hu

Hou-Yu Chen

Chi-On Chui

Yee-Chia Yeo

Yen-Ping Wang

Teng-Chun Tsai

Chih-Liang Chen

Pang-Yen Tsai

Tai-I Yang

Tzer-Min Shen

Yi-Bo Liao

Chi On Chui

Keng-Chu Lin

Kai-Hsuan Lee

Yi-Ming Sheu

Ling-Yen Yeh

Chih-Hung Chen

Cheng-Ting Chung

Wei-Sheng Yun

Yeur-Luen Tu

Wei-Yang Lee

Chung-Yi Yu

Cheng-Ta Wu

Wen-Chin Lee

Chun-Chieh Lin

Liang-Gi Yao

Ken-Ichi Goto

Chih-Ming Sun

Chia-Wei Su

Bo-Yu Lai

Huicheng Chang

Hun-Jan Tao

Sung-Li Wang

Li-Ting Wang

Cheng-Tung Lin

Wei-Jung Lin

Chun-Yen Chang

Hung-Chang Sun

Min-Hwa Chi

Yi-Hsuan Hsiao

Shih-Ting Hung

Kuo-Yin Lin

A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.

Fins disposed on stacks of nanostructures where the nanostructures are wrapped around by a gate

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Self-aligned metal gate for multigate device

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.

Semiconductor device

A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.

Semiconductor device fabrication methods and structures thereof

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

According to one example, a semiconductor device includes a first region comprising a plurality of nanosheets vertically stacked above a substrate, a second region comprising a fin protruding from the substrate, a first gate structure wrapping around each of the nanosheets, and a second gate structure disposed over the top surface and sidewalls of the fin. A top surface of a topmost nanosheet of the plurality of nanosheets is vertically offset from a top surface of the fin.

Semiconductor integrated circuit including gate-all-around FETs with nanosheet channels and Fin-like FETs

A semiconductor device structure is provided. The structure includes a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material. The structure also includes a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material, wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Semiconductor device structure

Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Semiconductor device structure and methods of forming the same

A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.

Semiconductor transistor device includes backside via electrically connecting epitaxial source/drain structures and method for forming the same

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Semiconductor device and method of forming thereof

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Semiconductor device structure and method for forming the same

A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

Transistors having vertical nanostructures

A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Nanosheet devices with hybrid structures and methods of fabricating the same

Growing community of inventors

Hsinchu County, Taiwan

Chih-Hao Wang