Mediatek Corporation

National Taiwan University

Mediatek Incorporation

Chih-Hao Sun

Hsiang-Hui Chang

Li-Shin Lai

Yi-Bin Lee

Shen-Iuan Liu

Shao-Yi Chien

Chi-Yao Yu

George Chien

Chih-Jung Chen

You-Ming Tsao

Augusto Marques

Po-Yun Hsiao

Chin-Yen Chao

Yu-Tsung Lo

Ka-Hang Lok

The present invention provides a receiver including a first band group, a second band group and a mixer. The first band group includes at least one LNA, wherein the first band group is configured to select one first LNA to receive a first input signal to generate an amplified first input signal. The second band group includes at least one LNA, wherein the second band group is configured to select one second LNA to receive a second input signal to generate an amplified second input signal. The first band group and the second band group are coupled to a first input terminal and a second input terminal of the mixer, respectively, and the mixer receives one of the amplified first input signal and the amplified second input signal to generate an output signal.

Band sharing technique of receiver

A communication unit includes a plurality of parallel radio frequency, RF, signal paths. Located between a first RF signal path of the plurality of parallel RF signal paths comprising at least one first RF amplifier and a second signal path comprising at least one second RF amplifier is one of a shared inductor or shared transformer. The at least one first RF amplifier is coupled to a supply voltage via a first switch and at least one second RF amplifier is coupled to the supply voltage via a second switch, and the first switch is closed that provides the supply voltage to the at least one second RF amplifier whilst the second switch is opened.

Transformer or inductor sharing in a radio frequency amplifier and method therefor

A signal processing circuit has a first mixer, a first amplifier, and a pulling effect mitigation circuit. The first mixer mixes a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor. The first amplifier amplifies the first output signal, and generates an amplified output signal at an output terminal of the first amplifier. The pulling effect mitigation circuit is coupled to the output terminal of the first amplifier, and generates a compensation signal to the output terminal for reducing at least an Nharmonic of the amplified output signal, wherein a value of N is equal to the frequency dividing factor.

Signal processing circuit for mitigating pulling effect and associated method

A signal modulator includes: a modulating circuit; a first signal trace block arranged to conduct a first in-phase oscillating signal to the modulating circuit, and conduct a first quadrature-phase oscillating signal to the modulating circuit; and a second signal trace block arranged to conduct a second in-phase oscillating signal to the modulating circuit, and conduct a second quadrature-phase oscillating signal to the modulating circuit, and a phase difference of the first in-phase oscillating signal caused by the first signal trace block substantially equals a phase difference of the second quadrature-phase oscillating signal caused by the second signal trace block, a second quadrature-phase oscillating signal to the modulating circuit, and a phase difference of the second in-phase oscillating signal caused by the second signal trace block substantially equals a phase difference of the first quadrature-phase oscillating signal caused by the first signal trace block.

Signal modulator and signal modulating method

A transmitter includes a first channel and a second channel. The first channel includes a first mixer, and is used for processing a first input signal to generate a first output signal; the second channel includes a second mixer, where the second channel does not receive any input signal. When the transmitter is operated under a first mode, both the first mixer and the second mixer receive oscillation signals.

Transmitter supporting two modes

An embodiment of the invention provides a sliced transmitter front-end (TX FE). The sliced TX FE includes first TX FE slices and a second TX FE slice that are connected in parallel. As a whole the first TX FE slices contributes a high-gain section to a superimposed gain range of the sliced TX FE. The second TX FE slice has a gain range that constitutes a low-gain section of the superimposed gain range of the sliced TX FE. A minimum gain of the gain range of the second TX FE slice is smaller than a minimum gain of the high-gain section.

Sliced transmitter front-end

A radio frequency (RF) modulator includes: converting means for up-converting a first and second baseband signals into a first and second up-converted signals with a reference clock, wherein a phase difference between the first and second baseband signals substantially equals 180&#xb0;/N; and combining means for combining the first and second up-converted signals to generate an output signal.

Radio frequency modulator and method thereof

A graphic processing unit (GPU) with a configurable filtering module (CFU) and an operation method thereof are presented. The graphic processing unit comprises a memory module and a configurable filtering module. The memory module stores at least one texture image. The configurable filtering module, connected to the memory module, comprises a plurality of filter equations, from which a filter equation is selected. A plurality of pixel points are sampled from the texture image. Each sampled pixel point is set with a weight value respectively. Each sampled pixel point with a weight value corresponding thereto is substituted into the selected filter equation to perform an operational process to acquire an operated value. Thereby, the user can decide the operation method of the GPU by selecting an appropriate filter equation and setting adjustable parameters in the filter equation.

Graphic processing unit (GPU) with configurable filtering module and operation method thereof

A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.

Growing community of inventors

Taipei, Taiwan

Chih-Hao Sun