Winbond Electronics Corporation

Asia Optical Co., Ltd.

Rexchip Electronics Corporation

Chih-Hao Lin

Yi-Tsung Tsai

Chia-Wei Wu

Chien-Chih Li

Wen-Ping Wang

Yi-Hui Chen

A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate.

Method for manufacturing DRAM

Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.

Memory device and method of forming the same

A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.

Methods for forming memory devices

A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

Non-volatile memory structure and manufacturing method thereof

Memory devices

A dynamic random access memory and its manufacturing method are provided. The memory includes a buried bit line, a plurality of buried word lines, a bit line contact structure, and a conductive plug. The buried bit line is formed in a substrate. A bottom surface of the buried word line is higher than a top surface of the buried bit line. The bit line contact structure is formed on the buried bit line and has a through hole. The bit line contact structure is not in direct contact with the buried bit line. A material of the bit line contact structure is different from a material of the buried bit line. The conductive plug is formed between the bit line contact structure and the buried bit line and fills the through hole, so that the bit line contact structure and the buried bit line are electrically connected.

DRAM and method for manufacturing the same

A dynamic random access memory (DRAM) structure is provided, and the DRAM structure includes a substrate, a DRAM, and a guard ring structure. The substrate includes a memory cell region. The DRAM is disposed in the memory cell region. The DRAM includes a capacitor contact coupled to a capacitor structure. The guard ring structure surrounds a border of the memory cell region. The capacitor contact and the guard ring structure originate from the same conductive layer.

Dynamic random access memory structure including guard ring structure

A manufacturing method of a dynamic random access memory (DRAM) structure includes following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A DRAM is formed in the memory cell region and includes a capacitor contact coupled to a capacitor structure. A transistor structure with a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a manufacturing process using a dummy gate. The capacitor contact and the dummy gate are formed by the same conductive layer.

Dynamic random access memory structure along with guard ring structure and manufacturing method thereof

A dynamic random access memory (DRAM) includes a substrate, isolation structures, buried word lines, bit lines, and capacitors. The substrate includes active areas configured into strips and arranged as an array. The isolation structures are disposed in trenches of the substrate. Each isolation structure is disposed between two adjacent active areas. The buried word lines are disposed in parallel in a first direction in the trenches. Each buried word line divides each active area arranged in the same column into a first contact region and a second contact region. The bit lines are disposed in parallel in a second direction on the substrate and across the buried word lines. A longitudinal direction of the active areas is non-orthogonal to the second direction. Each bit line is electrically connected with the first contact regions in the same row. The capacitors are electrically connected with the corresponding second contact regions respectively.

Dynamic random access memory

The present invention provides a dynamic random access memory (DRAM) including a plurality of transistors formed in a semiconductor substrate, wherein each of the transistors includes a vertical channel region. A plurality of bit line contained trenches is formed in the semiconductor substrate. Each of the bit line contained trenches comprises two bit lines, and each of the bit lines is electrically connected to an adjacent transistor. Each two sidewalls of each of the bit line contained trenches have a contact formed thereon. A plurality of word lines are formed over the plurality of bit lines and electrical connect to the plurality of transistors. Furthermore, a method for fabricating the DRAM is also provided.

Dynamic random access memory and method for fabricating the same

A lens device includes a base, a lens unit, a dividing plate, a cover plate, a shutter unit, and an actuator unit. The base has a front section with a front surface, a rear section with a rear surface, a lens hole, and a mounting space. The lens unit is disposed in the lens hole, and includes a lens. The dividing plate is mounted on the front section and has a first light hole. The cover plate is mounted on the front section and has a second light hole. The dividing plate and the cover plate define a working space therebetween. The shutter unit includes a first shutter piece pivotally disposed in the working space. The actuator unit is mounted in the mounting space, and includes a rotation portion, and an operating portion formed on the rotation portion and extending into the working space.

Lens device with an integrated shutter unit

A method for forming a buried split word line structure is provided. The method comprises the following steps. At first, a substrate having a trench therein is provided. Two liners are formed to a first thickness on sidewalls of the trench. Then, the trench is filled with a first insulating layer to a first height. The two liners are removed. Finally, a conductive material is deposited to a second height between and adjacent to the first insulating layer and the trench. Here, the first height is greater than the second height.

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Taichung, Taiwan

Chih-Hao Lin