Brocere Electronics Company Limited

Alcor Micro Corp.

Chih-Hao Lai

Jou-Hung Wang

Chi-Tung Chang

Chieh-Tsao Hwang

Yu-Hong Yang

Chih-Kai Huang

A modular IoT sensor system for Internet of things includes a network module and an expanded sensor module. The expanded sensor module includes a male connector and a female connector respectively disposed in two connection surfaces of the expanded sensor module, configured to detachably connect to a female connector of the network module. Shape and size of the female connector of the network module and the male connector and the female connector of the expanded sensor module conform to a USB type-C specification and pin definitions thereof are complied with a first pin definition different from USB type-C specification.

Modular wireless sensor architecture for internet of things

A enhanced DLL includes a delay chain, a phase detector and a delay control unit. The delay chain is arranged to delay a reference clock signal to generate a delayed reference clock signal and reflect the delay control setting on the delayed reference clock signal, wherein the delay chain is periodically reset according to a period of the reference clock signal. The phase detector is coupled to the delay chain, and arranged to detect a phase shift between the delayed reference clock signal and the reference clock signal, thereby to generate a control value. The delay control unit is coupled to the delay chain and the phase detector, and arranged to adjust the delay control setting based on the control value.

Enhanced harmonic lock free DLL for skew cancellation

A resistive random access memory device includes: a first control line, a second control line, a RRAM cell, a first programmable current source and a first programmable voltage source. The RRAM cell is coupled between the first control line and the second control line, and has a programmable resistive element. The first programmable current source is coupled to the first control line, and for selectively providing a configuration current to the RRAM cell. The first programmable voltage source is coupled to the first control line, and for selectively providing a configuration voltage to the RRAM cell. Additionally, a state of the programmable resistive element of the RRAM cell is configured according to the configuration current and the configuration voltage. Under architecture of the RRAM cell of the present invention, a reading circuit for the RRAM device can be implemented with a simple inverter instead of a complicated current sensing amplifier.

Controlling both current and voltage of resistive random access memory device

A frequency synthesizer applied to a frequency hopping system includes a voltage controlled oscillator (VCO), a phase lock loop (PLL) system, a second frequency divider, a first SSB mixer, a second SSB mixer, and a multiplexer. The VCO generates an oscillating frequency. The PLL system includes a first frequency divider and divides the oscillating frequency by 10 to generate a first dividing signal. The second frequency divider divides the oscillating frequency by 2 to generate a second dividing signal and further divides the second dividing signal by 2 to generate a third dividing signal. The first SSB mixer mixes frequencies of the second and third dividing signals to generate a first mixing signal. The second SSB mixer mixes frequencies of the first mixing signal and the first dividing signal to generate a second mixing signal. The Multiplexer determines to output the first mixing signal or the second mixing signal.

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Taipei, Taiwan

Chih-Hao Lai