Nan Ya Technology Corporation

Chih-Hao Kuo

Ching-Yuan Kuo

Chih-Wei Huang

Hsu-Cheng Fan

The disclosure provides a method for fabricating a semiconductor structure with strengthened patterns. The method includes forming a masking layer on the substrate, the masking layer including a peripheral region and an array region adjacent to the peripheral region; forming a first etched peripheral pattern in the peripheral region and a first etched array pattern in the array region, wherein the first etched peripheral pattern and the first etched array pattern have a top surface, a sidewall and a bottom surface, the sidewall connecting the top surface to the bottom surface; forming a second peripheral pattern on the first etched peripheral pattern and forming a second array pattern on the first etched array pattern; and etching the masking layer using the first etched peripheral pattern and the second peripheral pattern as an etching mask to form an etched masking layer in the peripheral region.

Method for fabricating semiconductor structure with strengthened patterns

A semiconductor structure includes a substrate, a bit line, a dielectric layer and a word line. The substrate has an active area and a trench. The bit line is on the substrate and extends along a direction. The active area includes a first portion and a second portion respectively located at two opposite sides of the bit line and spaced apart from each other along the direction. A landing area extends from the first portion of the active area to the second portion of the active area across the bit line. A dielectric layer is in the trench. The active area is surrounded by the dielectric layer. The word line is surrounded by the dielectric layer. The word line is curved and below the bit line. A portion of the word line is between first and second end portions of the landing area.

Semiconductor structure having a landing area extends from first portion to second portion of an active area across a bit-line

The disclosure provides a double patterning technology to define peripheral patterns in a DRAM cell. Due to the consideration of line width, the peripheral pattern lines need to undergo two lithographic processes and two etch processes. The presence of additional photoresist patterns in the array region while fabricating peripheral patterns on the M0 layer can increase the stability of peripheral pattern lines. Peripheral pattern lines will not collapse after being subjected to the rinse of developing agent. Moreover, the photoresist coverage of patterns in the array region is not excessive, so the loading effect during etch processes is reduced and the occurrence of photoresist residues is avoided.

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Taoyuan, Taiwan

Chih-Hao Kuo