Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Hao Hsieh

Dian-Hau Chen

Chung-Yi Lin

Ko-Bin Kao

Hsiang-Lin Chen

Jiing-Feng Yang

Yung-Shih Cheng

Tzu-Hao Huang

Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

Methods of patterning small via pitch dimensions

Growing community of inventors

Taipei, Taiwan

Chih-Hao Hsieh