Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

Au Optronics Corporation

Industrial Technology Research Institute

Other

National Taiwan University

Nuvoton Technology Corporation

Gogoro Inc.

Elite Semiconductor Microelectronics Technology Inc.

Chih-Hao Chen

Chao-Hsing Chen

Wen-Yen Chen

Jiann-Horng Lin

Tai-Yen Peng

Chung-Chi Ko

Hsin-Ying Wang

Ming-Chung Liang

Hsin-Yi Tsai

Chi-Shiang Hsu

Ying-Hao Wu

Keng-Chu Lin

Seok-Lyul Lee

Cheng-Li Fan

Tze-Liang Lee

Szu-Wei Lu

Jui-Pin Hung

Li-Hui Cheng

Tsun-Kai Ko

Chen Ou

Yi-Hung Lin

Jia-Kuen Wang

Chii-Ping Chen

Wei-Chih Peng

Chien-Chih Liao

Cheng-Lin Lu

Wu-Tsung Lo

Yi-Lin Tsai

I-Lun Ma

Meng-Hsiang Hong

Kuo-Ching Hung

Yi-Lun Chou

Yi-Chang Lee

Chao-Kuei Yeh

Jing-Cheng Lin

Meng-Sheng Chang

Po-Hsiang Huang

Shao-Yu Chou

Chin-Fu Kao

Shing-Chyang Pan

Cha-Hsin Chao

Chung Yu Wang

Jung-Hau Shiu

Chia Cheng Chou

Shu-Huei Suen

Kung-Chen Yeh

Long Hua Lee

Hom-Ti Lee

Hou-Peng Wan

Chun-Kai Chen

An-Jiao Fu

Liang-Yin Huang

Chun-Hsing Su

Chih-Ming Wang

Schang-Jing Hon

Hsien-Wen Liu

Yu-Yu Chen

Chia-Cheng Chou

Syuan-Ling Yang

Ta-Ching Yu

Tzu-Li Lee

Min-Hsuan Chiu

Ping-Yin Hsieh

Yung-Hsiang Lin

Chun-Teng Ko

Liang-Sheng Chi

Wei-Jung Chung

Chiung-Fang Liu

Yu-Yao Lin

Horng-Huei Tseng

Kei-Wei Chen

Ying-Lang Wang

Yi-Wei Chiu

Jyu-Horng Shieh

Chih-Jen Hu

Chih-Ming Chang

Kuang-Yuan Hsu

Chih-Kung Lee

Chin-Chuan Chang

Po-Cheng Shih

Yu-Chi Lin

Yuh-Jier Mii

Hung Jui Chang

Yi-Chao Mao

Wen-Ying Wen

Ding-Zheng Lin

Chia-Hao Chang

Wen-Kuo Hsieh

Chao-Yen Lin

Te-Ming Kung

Po-Ju Chen

Ruey-Fu Shih

Tsung-Dar Cheng

Shih-Yi Syu

Yi-Tsang Hsieh

Kuo-Yung Hung

Chih-Chun Pei

Pei-Wen Huang

Lai Chien Wen

Heng-Ying Cho

A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.

Plasma processing apparatus and method

A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.

Reduction of line wiggling

A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.

Semiconductor device having fuse array and method of making the same

A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength λ; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness.

Light-emitting device

A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate, and the first semiconductor layer adjacent to the second edge includes a second sidewall separated from the second side surface of the substrate by a distance.

Light-emitting device with a plurality of concave parts on the edge of the semiconductor mesa

A light-emitting device includes a first semiconductor layer; a semiconductor pillar formed on the first semiconductor layer, including a second semiconductor layer and an active layer, wherein the semiconductor pillar comprises an outmost periphery; a first contact layer formed on the first semiconductor layer and including a first contact portion and a first extending portion, wherein the first extending portion continuously surrounds an entirety of the outmost periphery of the semiconductor pillar and the first contact portion; a second contact layer formed on the second semiconductor layer; a first insulating layer including multiple first openings exposing the first contact layer and multiple second openings exposing the second contact layer; a first electrode contact layer connected to the first contact portion through the multiple first openings and covering all of the first contact layer; a second electrode contact layer connected to the second contact layer through the multiple second openings.

A light-emitting device comprises a substrate comprising a top surface and a sidewall; a semiconductor stack formed on the top surface of the substrate comprising a first semiconductor layer, an active layer and a second semiconductor layer; a dicing street surrounding the semiconductor stack and exposing the top surface of the substrate; a protective layer covering the semiconductor stack and the dicing street; a reflective layer comprising a Distributed Bragg Reflector structure and covering the protective layer; and a cap layer covering the reflective layer, wherein the reflective layer comprises an uneven portion adjacent to the sidewall of the substrate, and the uneven portion comprises an uneven thickness.

A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Package structure and manufacturing method thereof

Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.

Patterning methods for semiconductor devices and structures resulting therefrom

A light-emitting device comprises a substrate comprising a sidewall, a first top surface, and a second top surface, wherein the second top surface is closer to the sidewall of the substrate than the first top surface to the sidewall of the substrate; a semiconductor stack formed on the substrate comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a dicing street surrounding the semiconductor stack, and exposing the first top surface and the second top surface of the substrate; a protective layer covering the semiconductor stack; a reflective layer comprising a Distributed Bragg Reflector structure covering the protective layer; and a cap layer covering the reflective layer, wherein the second top surface of the substrate is not covered by the protective layer, the reflective layer, and the cap layer.

A display panel includes a first substrate, an electrode layer, and a display medium layer. The electrode layer is disposed on the first substrate. The display medium layer is disposed on the electrode layer and includes a filler and liquid crystal capsules. The liquid crystal capsules are distributed in the filler, and the filler has a birefringence difference &#x394;n in a range from 0.02 to 0.175.

Display panel

A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.

Semiconductor device and method of forming thereof

Growing community of inventors

Hsinchu, Taiwan

Chih-Hao Chen