Taiwan Semiconductor Manufacturing Comp. Ltd.

Quanta Computer Incorporated

Mstar Semiconductor, Inc.

Industrial Technology Research Institute

Tsinghua University

Au Optronics Corporation

Realtek Semiconductor Inc.

Mosaid Technologies Corporation

National Chung Cheng University

Marvell International Limited

Mediatek Corporation

Lite-on Technology Corporation

Lite-on Electronics (guangzhou) Limited

Metal Industries Research & Development Centre

China Medical University

Chih-Hao Chang

Jeff J Xu

Wen-Huei Guo

Hao-Yi Tsai

Tsung-Lin Lee

Shou-Zen Chang

Jen-Hsiang Lu

Chung-Ting Li

Chih-Hsin Ko

Tung Ying Lee

Chun Feng Chang

Feng Yuan

Ming-Feng Shieh

Shao-Ming Yu

Chang-Yun Chang

Yi-Tang Lin

Hsin-Chih Chen

Kai-Tai Chang

Kuei-Liang Lu

Clement Hsingjen Wann

Tin-Hao Kuo

Tsung-Hsien Chiang

Hsin-Chieh Lin

Yu-Chih Huang

Chien-Hsun Wang

Chia-Hung Liu

Chih-Hsiang Chang

Tsai-Fu Wu

Po-Chun Lin

Bi-Fen Wu

Yaw-Tzorng Tsorng

Hung-Ming Chen

Chih-Hao Yu

Cheng-Yu Hsieh

Jeffrey Junhao Xu

Chin-Hsiang Lin

Chih Chieh Yeh

Yasutoshi Okuno

Sey-Ping Sun

Shih-Wei Chen

I-Ming Chang

Yi-Shien Mor

Shou Zen Chang

Chun-Ti Lu

Chen-Hua Douglas Yu

Chung-Shi Liu

Zhiqiang Wu

Wen-Hsing Hsieh

Chih-Hsuan Tai

Chen-Nan Yeh

Min-Lin Lee

Jui-Chien Huang

Chien-Ling Hwang

Andrew Joseph Kelly

Hsin-Hung Liao

Guan-Yu Chen

Shih-Hsien Wu

Ying-Cheng Tseng

Wei Sen Chang

Ban-Li Wu

Cheng-Long Chen

Shinn-Juh Lay

Wei-Sen Chang

Chin-Yuan Lo

Jhon Jhy Liaw

Yu-Ming Lin

Chung-Ju Lee

Chih-Sheng Chang

Tien-Lu Lin

Chun-Sheng Liang

Liang-Gi Yao

Yu-Kai Chen

Ta-Chun Lin

Han-Liang Chou

Tung-Hsing Wu

Chih-Wei Yang

Ting-Chu Ko

Che-Chih Chang

Show-An Chen

Nan-Chin Chuang

Yi-Wen Chen

Yung-Hsiang Liu

Tung-Lin Tsai

Chung-Hsien Chen

Yung-Sheng Tsai

Chun-Chieh Tseng

Yue-Jun Wang

Chih-Lung Lin

Ting-Kuang Pao

Hsu-Shen Chu

Jiun-In Guo

Chia-Lin Chuang

Chia-Jung Wu

Cheng-Chieh Weng

Li-Wen Weng

Yu-Jen Wu

Shih-Lun Lai

Chun-Mu Chen

Yuan-Chang Fann

Cheng-Ting Shih

A method includes forming a first gate spacer and a second gate spacer on a sidewall of a first gate structure. The first gate spacer is between the second gate spacer and the first gate structure. A first interlayer dielectric (ILD) layer is formed to surround the first gate spacer, the second gate spacer, and the first gate structure. A portion of the second gate spacer and a portion of the first ILD layer are removed simultaneously. A top surface of the second gate spacer is lower than a top surface of the first ILD layer.

Method for forming semiconductor device

A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Semiconductor structure with high integration density and method for manufacturing the same

The present disclosure provides a system and method for enabling cableless connections within a server system. The server system comprises a motherboard (MB) module, a power distribution board (PDB) module, power supply unit (PSU) modules, network interface controller (NIC) modules, fan modules, graphic process unit (GPU) modules, and a hyperscale GPU accelerator (HGX) platform. These components of the server system are interconnected by a plurality of circuit boards. The plurality of circuit boards includes, but is not limited to, a main board, linking boards (BDs), a PDB, a fan board, a power linking board, peripheral-component-interconnect-express (PCIe) expander boards, a plurality of NVLink bridges, and HGX base boards.

Application and integration of a cableless server system

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

Semiconductor package and manufacturing method thereof

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Method for fabricating a strained structure and structure formed

A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Structure and method for providing line end extensions for fin-type active regions

A video encoding method includes: during a first period, performing an encoding process upon a first block group of a current frame to generate a first block group bitstream; and during a second period, transmitting a second block group bitstream derived from encoding a second block group of the current frame, wherein the second period overlaps the first period. The encoding process includes: during a first time segment of the first period, performing a first in-loop filtering process upon a first group of pixels; and during a second time segment of the first period, performing a second in-loop filtering process upon a second group of pixels, wherein the second time segment overlaps the first time segment, and a non-zero pixel distance exists between a first edge pixel of the first group of pixels and a second edge pixel of the second group of pixels in a filter direction.

Video encoding method using multiple in-loop filters in low latency video encoding and associated video encoding apparatus

A cover for covering an opening of a socket formed by a housing comprises a body; one or more bosses extending from the body, a first locking mechanism, a second locking mechanism, and a release tab. The bosses movably couple the body to the housing such that the body is movable between first and second positions. The first locking mechanism releasably attaches to the housing to secure the body in the first position. The second locking mechanism releasably attaches to the housing to secure the body in the second position. The release tab aids in detaching the first locking mechanism from the first wall and the second locking mechanism from the second wall. When the body is in the first position, the body allows access to the socket through the opening. When the body is in the second position, the body prevents access to the socket through the opening.

Cover for socket of fan wall

A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.

Semiconductor package and forming method thereof

An implant guide system for hip replacement surgery includes an angle guide member and a first positioning plate. The angle guide member has a body and a protrusion that are substantially connected to each other. The body has a curved surface corresponding in shape to a surface of a patient's acetabulum. The protrusion has a first through hole extending to the body. An acute angle is defined between an extension line of the first through hole and a flat surface of the body. The first positioning plate has a first holding portion and a first spacing portion that are substantially connected to each other. The first spacing portion has a second through hole, a third through hole and a fourth through hole that are parallel to each other.

Implant guide system for hip replacement surgery

A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure. The semiconductor die is located over the base substrate and laterally arranged next to the second redistribution circuit structure.

Circuit substrate, package structure and method of manufacturing the same

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Gate spacer structure of FinFET device

Growing community of inventors

Chu-Bei, Taiwan

Chih-Hao Chang