Taiwan Semiconductor Manufacturing Comp. Ltd.

Quanta Computer Incorporated

Mstar Semiconductor, Inc.

Industrial Technology Research Institute

Tsinghua University

Au Optronics Corporation

Realtek Semiconductor Inc.

National Chung Cheng University

Marvell International Limited

Lite-on Technology Corporation

Mosaid Technologies Corporation

Lite-on Electronics (guangzhou) Limited

Metal Industries Research & Development Centre

Insight Medical Solutions Inc.

Chih-Hao Chang

Jeff J Xu

Wen-Huei Guo

Hao-Yi Tsai

Tsung-Lin Lee

Shou-Zen Chang

Chih-Hsin Ko

Tung Ying Lee

Jen-Hsiang Lu

Chung-Ting Li

Chun Feng Chang

Feng Yuan

Clement Hsingjen Wann

Tin-Hao Kuo

Ming-Feng Shieh

Shao-Ming Yu

Chang-Yun Chang

Yi-Tang Lin

Tsung-Hsien Chiang

Hsin-Chih Chen

Kai-Tai Chang

Hsin-Chieh Lin

Kuei-Liang Lu

Yu-Chih Huang

Chien-Hsun Wang

Chih-Hsiang Chang

Chia-Hung Liu

Tsai-Fu Wu

Po-Chun Lin

Bi-Fen Wu

Yaw-Tzorng Tsorng

Hung-Ming Chen

Chih-Hao Yu

Cheng-Yu Hsieh

Jeffrey Junhao Xu

Chin-Hsiang Lin

Chih Chieh Yeh

Yasutoshi Okuno

Sey-Ping Sun

Shih-Wei Chen

I-Ming Chang

Yi-Shien Mor

Shou Zen Chang

Chun-Ti Lu

Chao-An Jong

Jyun-Yang Shen

Sheng-Yu Chang

Yi-Fu Liu

Chen-Hua Douglas Yu

Chung-Shi Liu

Zhiqiang Wu

Wen-Hsing Hsieh

Chih-Hsuan Tai

Min-Lin Lee

Chen-Nan Yeh

Chien-Ling Hwang

Andrew Joseph Kelly

Hsin-Hung Liao

Jui-Chien Huang

Guan-Yu Chen

Shih-Hsien Wu

Ying-Cheng Tseng

Wei Sen Chang

Ban-Li Wu

Cheng-Long Chen

Shinn-Juh Lay

Wei-Sen Chang

Chin-Yuan Lo

Yu-Ming Lin

Chung-Ju Lee

Chih-Sheng Chang

Tien-Lu Lin

Liang-Gi Yao

Yu-Kai Chen

Chih-Wei Yang

Ting-Chu Ko

Che-Chih Chang

Show-An Chen

Nan-Chin Chuang

Yung-Hsiang Liu

Tung-Lin Tsai

Yung-Sheng Tsai

Chung-Hsien Chen

Chun-Chieh Tseng

Yue-Jun Wang

Ting-Kuang Pao

Jiun-In Guo

Hsu-Shen Chu

Chih-Lung Lin

Chia-Lin Chuang

Cheng-Chieh Weng

Chia-Jung Wu

Li-Wen Weng

Yu-Jen Wu

Chun-Mu Chen

Shih-Lun Lai

Yuan-Chang Fann

Wen-Hui Peng

Shih-Hua Huang

Che-Chen Wu

The present disclosure provides a system and method for enabling cableless connections within a server system. The server system comprises a motherboard (MB) module, a power distribution board (PDB) module, power supply unit (PSU) modules, network interface controller (NIC) modules, fan modules, graphic process unit (GPU) modules, and a hyperscale GPU accelerator (HGX) platform. These components of the server system are interconnected by a plurality of circuit boards. The plurality of circuit boards includes, but is not limited to, a main board, linking boards (BDs), a PDB, a fan board, a power linking board, peripheral-component-interconnect-express (PCIe) expander boards, a plurality of NVLink bridges, and HGX base boards.

Application and integration of a cableless server system

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

Semiconductor package and manufacturing method thereof

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Method for fabricating a strained structure and structure formed

A cover for covering an opening of a socket formed by a housing comprises a body; one or more bosses extending from the body, a first locking mechanism, a second locking mechanism, and a release tab. The bosses movably couple the body to the housing such that the body is movable between first and second positions. The first locking mechanism releasably attaches to the housing to secure the body in the first position. The second locking mechanism releasably attaches to the housing to secure the body in the second position. The release tab aids in detaching the first locking mechanism from the first wall and the second locking mechanism from the second wall. When the body is in the first position, the body allows access to the socket through the opening. When the body is in the second position, the body prevents access to the socket through the opening.

Cover for socket of fan wall

A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.

Semiconductor package and forming method thereof

A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

Method for forming semiconductor device

A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure. The semiconductor die is located over the base substrate and laterally arranged next to the second redistribution circuit structure.

Circuit substrate, package structure and method of manufacturing the same

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Gate spacer structure of FinFET device

A release mechanism is disclosed that can facilitate safely and efficiently removing an expansion card from a computing device. The release mechanism can be installed on a motherboard around an expansion slot, and can include an opening that permits access to the expansion slot to allow an expansion card to be installed therein. When removal of the expansion card is desired, a handled of the release mechanism can be pulled, causing contact surfaces of the release mechanism to push the expansion card away from the expansion slot with even force, removing the need to tilt the expansion card.

Facilitated expansion card removal

A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Structure and method for providing line end extensions for fin-type active regions

A fan assembly includes a socket to receive a fan module, a fan flap coupled to a first side wall of the socket, and an anti-reflow device coupled to a second side wall of the socket. The fan flap moves in a curved path between a first position and a second position. The anti-reflow device has an attachment feature, an embossed feature, and a stopping feature. The attachment feature attaches the anti-reflow device to the second side wall. The embossed feature extends through a first aperture in the second side wall. The stopping feature extends through a second aperture in the second side wall and contacts the fan flap. When the fan module is removed, the stopping feature retains the fan flap in the first position to block the socket and prevent air from reflowing through the socket.

Mechanism for preventing reflow for fan flap failure

Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

Semiconductor devices having fin field effect transistor (FinFET) structures and manufacturing and design methods thereof

A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

Semiconductor device and a method for fabricating the same

Growing community of inventors

Chu-Bei, Taiwan

Chih-Hao Chang