Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Feng Huang

Kuo-Su Huang

Shun-Liang Hsu

Shih-Feng Huang

P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N&minus; silicon onto the P&minus; substrate with an additional process step in which a buried N&plus; layer is formed at the surface of the substrate by ion implantation. This N&plus; buried layer significantly reduces the width of the depletion layer that extends outwards from the P&minus; well when voltage is applied to the drain thus substantially raising the punch-through voltage.

P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture

A pattern for monitoring epitaxial layer washout is disclosed. The pattern includes first and second sub-patterns. The first sub-pattern has a shape and defines one or more minimum dimensions. Obfuscation of the first sub-pattern means that epitaxial washout has occurred at least for dimensions equal to or less than the minimum dimensions. The second sub-pattern has the same shape of the first sub-pattern, but defines one or more maximum dimensions. Obfuscation of the second sub-pattern means that epitaxial washout has occurred for dimensions equal to or less than the maximum dimensions. The sub-patterns can include a pair of separated features, such as a pair of interlocking but separated L-shaped features, the separation of which defines the dimensions of the sub-patterns.

Pattern for monitoring epitaxial layer washout

The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N&minus;regions instead of the single epitaxial N&minus;region that is used by devices of the prior art. The resistivities and thicknesses of these two N&minus;regions are chosen so that their mean resistivity is similar to that of the aforementioned single N&minus;layer. A key feature is that the lower N&minus;layer (i.e. the one closest to the P&minus;substrate) has a resistivity that is greater than that of the upper N&minus;layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on-resistance. A process for manufacturing the device is also described.

LDMOS device with double N-layering and process for its manufacture

The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N&minus; regions instead of the single epitaxial N&minus; region that is used by devices of the prior art. The resistivities and thicknesses of these two N&minus; regions are chosen so that their mean resistivity is similar to that of the aforementioned single N&minus; layer. A key feature is that the lower N&minus; layer (i.e. the one closest to the P&minus; substrate) has a resistivity that is greater than that of the upper N&minus; layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on resistance. A process for manufacturing the device is also described.

Method of forming LDMOS device with double N-layering

A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate. A subsequent anneal procedure results in the formation of a N well region, in the first portion of the semiconductor substrate, self-aligned to the formed P well region, located in the second portion of the semiconductor substrate.

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Chu-Pei, Taiwan

Chih-Feng Huang