Tsinghua University

Richtek Technology Corporation, R.o.c

Richtek Technology Corporation

Macroblock, Inc.

Chih-Fang Huang

Ting-Fu Chang

Tsung-Yi Huang

Chien-Wei Chiu

Tsung-Yu Yang

Tsung-Chieh Hsiao

Po-Chin Peng

Ya-Hsien Liu

Jheng-Yi Jiang

Chia-Hui Cheng

Kung-Yen Lee

Wei-Yu Chen

Hung-Der Su

Chun-Hung Wu

Jenn-Chang Hwang

Wei-Chen Yang

Shao-Yen Chiu

Keh-Yung Cheng

Yu-Li Wang

Sheng-Chung Wang

Hua-Chih Hsu

Sheng-Zhong Wang

K C Chang

Chien-Cheng Chen

Sheng-Hong Wang

Yi-Chen Li

Jia-Wei Hu

You-An Lin

Yong-Shiang Jan

Jia-Qing Hung

A semiconductor structure includes: a U-metal-oxide-semiconductor field-effect transistor (UMOS) structure; and a trench junction barrier Schottky (TJBS) diode, wherein an insulating layer of a sidewall of the TJBS diode does not have a side gate.

Semiconductor structure with trench junction barrier schottky (TJBS) diode

A structure and a manufacturing method of a metal-oxide-semiconductor field-effect transistor with an element of IVA group ion implantation are disclosed. The element of IVA group ion implantation layer is disposed in a body and close to an interface between a gate oxide layer and the body. The element of IVA group ion implantation layer is utilized to change a property of a channel of the structure.

Structure and a manufacturing method of a MOSFET with an element of IVA group ion implantation

A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.

Structure of trench metal-oxide-semiconductor field-effect transistor

A power semiconductor device includes a substrate, a main body and an electrode unit. The main body includes an active portion, an edge termination portion surrounding the active portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes a first-type semiconductor region, and a plurality of spaced-apart second-type semiconductor segments distributed in the first-type semiconductor region and arranged at intervals along a Y-direction directing from the insulating layer toward the substrate, and an X-direction directing from the active portion toward the edge termination portion. The electrode unit includes a first electrode and a second electrode.

Power semiconductor device

A power semiconductor device includes a substrate, a main body, and an electrode unit. The main body includes an active portion disposed on the substrate, an edge termination portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes first-type semiconductor region, a second-type semiconductor region and a top surface. The first-type semiconductor region is adjacent to the active portion and has a first-type doping concentration decreased from the top surface toward the substrate. The electrode unit includes a first electrode disposed on the insulating layer, and a second electrode disposed on the substrate.

A structure of high electron mobility light emitting transistor comprises a substrate, a HEMT region disposed on the substrate, and a gallium nitride LED (GaN-LED) region disposed on the substrate. A two-dimensional electron gas layer is present in each of the HEMI region and the LED region, and the HEMT region is coupled to the LED region through the two-dimensional electron gas layer.

Structure of high electron mobility light emitting transistor

A semiconductor structure comprises a substrate, an epitaxial layer, an active area and a termination. The substrate has a first conducting type of semiconductor material. The epitaxial layer disposed on the substrate has a first conducting type of semiconductor material. The active area is a working area of the semiconductor structure. The termination protects the active area. The termination has a junction termination extension (JTE) having a second conducting type of semiconductor material. The counter-doped area is disposed in the JTE area and has the first conducting type of semiconductor material. A dose of the first conducting type of semiconductor material in the counter-doped area increases along one direction.

Semiconductor structure

The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate and manufacturing method thereof

Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate

The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Junction barrier Schottky diode and manufacturing method thereof

The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

High electron mobility transistor and manufacturing method thereof

The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

A method of fabricating a silicon carbide (SiC) layer is disclosed, which comprises steps: (S) heating a silicon-based substrate at a temperature of X &#xb0; C.; (S) carburizating the silicon-based substrate with a first hydrocarbon-containing gas at a temperature of Y &#xb0; C. to form a carbide layer on the silicon-based substrate; (S) annealing the silicon-based substrate with the carbide layer thereon at a temperature of Z &#xb0; C.; and (S) forming a silicon carbide layer on the carbide layer with a second hydrocarbon-containing gas and a silicon-containing gas at a temperature of W &#xb0; C.; wherein, X is 800 to 1200; Y is 1100 to 1400; Z is 1200 to 1500; W is 1300 to 1550; and X&#x3c;Y&#x2266;Z&#x2266;W. In the method of the present invention, since no cooling steps between respective steps are required, the full process time can be reduced and the cost is lowered because no energy consumption occurs for the cooling and the re-heating steps.

Growing community of inventors

Hsinchu, Taiwan

Chih-Fang Huang