National Applied Research Laboratories

National Chip Implementation Center National Applied Research Laboratories

National Chip Implementation Center

Chih-Chyau Yang

Chun-Ming Huang

Chien-Ming Wu

Shih-Lun Chen

Chin-Long Wey

Chi-sheng Lin

Chi-Shi Chen

Chun-Yu Chen

Kuen-Jong Lee

Hui-Ming Lin

Jing-Yang Jou

Lan-Da Van

A vehicle idle-speed warning system and vehicle idle-speed detection method thereof are provided. It is non-invasive, that is, there is no need to change or modify any part of the constructing parts in the engine compartment. The present invention can be adopted stand-alone, or be applied to existing popular apparatuses, such as GPS, driving recorders, smart handheld devices, and vehicle electronic equipments. With the composing elements of a motion information module, an input module, an output module, a timer module and an information processing module, the present invention can accurately determine whether the vehicle under surveillance is in idle state and for how long it is in the idle state, and send an alarm signal automatically. With the implementation of the present invention, drivers can always be alarmed with the vehicle idling situations to prevent possible dangers or coming tickets due to the violation of traffic regulations in certain countries.

Vehicle idle-speed warning system and idle-speed detection method

A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

Three-dimensional SoC structure formed by stacking multiple chip modules

A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

Multi-layer SoC module structure

A socket structure stack and a socket structure thereof are provided. The socket structure stack includes at least two socket structures, and each socket structure includes a main body, a plurality of conductive elements, and a plurality of connecting elements. The main body includes an inner plate and an outer plate, wherein the inner plate has a receiving portion and an embedded portion. The conductive elements are embedded in the embedded portion, and the connecting elements are mounted on the outer plate so as to connect adjacent socket structures together. The socket structures are so configured that ICs, processors, and printed circuit boards connected to the socket structures or the socket structures themselves can be recycled. Moreover, the printed circuit boards can be easily assembled to the socket structures, and the socket structures can be stacked up and securely connected to form a 3D structure which is otherwise difficult to put together by soldering.

Socket structure stack and socket structure thereof

A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

Multi-project system-on-chip and its method

Growing community of inventors

Hsinchu, Taiwan

Chih-Chyau Yang