Chang Chun Petrochemical Co., Ltd.

United Microelectronics Corp.

Schweitzer Biotech Company Ltd.

Chih-Chung Wu

Yao-Sheng Lai

Jui-Chang Chou

Huei-Fang Huang

Yi-Ching Wu

Tzu-Hung Yang

Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface, which are analyzed by grazing incidence X-ray diffraction (GIXRD), and each have an intensity of a characteristic peak of (111) plane denoted by I, an intensity of a characteristic peak of (200) plane denoted by I, an intensity of a characteristic peak of (220) plane denoted by I, an FWHM of the characteristic peak of (111) plane denoted by W, and an FWHM of the characteristic peak of (200) plane denoted by W. The first and second surfaces each have a ratio of (I+I)/(I+I+I) of 0.83 or more and a value of (W+W) of 0.80° or less. By controlling the features, it can improve the corrosion resistance of the electrolytic copper foil and further increase the safety of the lithium-ion cell.

Electrolytic copper foil and electrode and lithium-ion cell comprising the same

Device for extracting and amplifying nucleic acid

Provided are an electrodeposited copper foil, an electrode comprising the same, and a lithium-ion secondary battery comprising the same. The electrodeposited copper foil has a drum side and a deposited side opposing the drum side, wherein at least one of the drum side and the deposited side exhibits a void volume value (Vv) in the range of 0.17 &#x3bc;m/&#x3bc;mto 1.17 &#x3bc;m/&#x3bc;m; and an absolute value of a difference between a maximum height (Sz) of the drum side and a Sz of the deposited side is in the range of less than 0.60 &#x3bc;m.

Electrodeposited copper foil and electrode, and lithium-ion secondary battery comprising the same

A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.

Method for planarizing semiconductor devices

Growing community of inventors

Taipei, Taiwan

Chih-Chung Wu