Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Chung Huang

Chi-Ming Tsai

Dong-Hsu Cheng

Ming-Ho Tsai

Yung-Hsiang Chen

Chih-Chiang Tu

Jyun-Hong Chen

Sheng-Wen Huang

Jia-Guei Jou

Wei-Lin Chu

Hsin-Lun Tseng

Ru-Gun Liu

Tsai-Sheng Gau

Wen-Chun Huang

Chung-Hung Lin

Ming-Hui Chih

Chia-Ping Chiang

Ching-Hung Lai

Kuan-Chi Chen

Yen-Tung Hu

Yi-Chiuan Luo

Ya-Hsuan Wu

Yung-Pei Chin

Shiuan-Li Lin

A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.

Method and system for layout enhancement based on inter-cell correlation

The present disclosure provides a method and a system for generating photomask patterns. The system obtains a design layout image, and generates a hotspot image corresponding to the design layout image based on a hotspot detection model. The system generates two photomask patterns based on the hotspot image. The at least two photomask patterns are transferred onto a semiconductor substrate.

Method and system for generating photomask patterns

A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.

A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 &#x3bc;mto 60000 &#x3bc;m. The second pattern has an area of 0.16 &#x3bc;mto 60000 &#x3bc;m. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.

Mask and photolithography system

A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value.

Apparatus and method for e-beam writing

The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron&#xd7;10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Structure and method for E-beam in-chip overlay mark

A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Layout decomposition method

Growing community of inventors

Hsinchu, Taiwan

Chih-Chung Huang