Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Mediatek Corporation

Chih-Chung Chiu

Chih-Han Lin

Shih-Yao Lin

Kuei-Yu Kao

Chen-Ping Chen

Chao-Cheng Chen

Ming-Ching Chang

Ke-Chia Tseng

Yu-Lin Chao

Chen-Yui Yang

Hsien-Chung Huang

Yan-Fu Jhou

Ke-Horng Chen

Chun-Kai Liu

Ming-Ji Dai

Chien-Chih Lin

Puo-Yu Chiang

Yan-Liang Ji

Heng-Chieh Chien

Shu-Jung Yang

Chih-Ming Shen

Zheng Zeng

Chih-Ming Tzeng

Chu-Wei Hu

Ming-Kaan Liang

Cheng-Hua Lin

Chi-Chung Liao

Li-Ling Liao

Chih-Chang Lee

Hung-Yi Teng

Shou-Chung Hsieh

Chih-Cheng Wu

Sheng-Hung Fan

Wei-Li Tsao

Ming-Ching Chiang

A method for fabricating a semiconductor device is provided. The method includes forming a fin structure extending along a first lateral direction; forming a dummy gate structure that is over a portion of the fin structure and extends along a second direction perpendicular to the first lateral direction; growing source/drain structures that are respectively coupled to ends of the portion of the fin structure; removing the dummy gate structure to form a gate trench; lining inner sidewalls of the gate trench with a gate spacer; and forming an active gate structure in the gate trench.

Gate structures and spacers in semiconductor devices and methods of manufacturing thereof

A voltage conversion device includes a filter circuit, a first inductor, a second inductor a first conversion module, a second conversion module, and a control circuit. The filter circuit is electrically connected to a first AC terminal and a second AC terminal. The first inductor is electrically connected to the first AC terminal and a first conversion terminal. The second inductor is electrically connected to the second AC terminal and a second conversion terminal. The first conversion module is electrically connected to a first DC voltage terminal, a second DC voltage terminal, and the first conversion terminal. The second conversion module is electrically connected to the first DC voltage terminal, the second DC voltage terminal, and the second conversion terminal. The control circuit transmits switch-control signals to the first conversion module and the second conversion module. A voltage conversion method is used with the voltage conversion device.

Voltage conversion device and voltage conversion method thereof

A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Semiconductor devices and methods of fabrication thereof

A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Semiconductor devices including dummy gate dielectric layer and methods of manufacturing thereof

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Semiconductor device including gate spacer with tilted portion and method of manufacturing thereof

The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Multi-channel devices and methods of manufacture

A driving method for a multiple frequency coupling generator is provided. The method includes: in normal operations, interpreting an input digital control signal transmitted from a digital signal processor into an interpreted digital control signal; interpreting the interpreted digital control signal into a plurality of magnetic coupling signals by a magnetic coupling switch circuit; performing signal recovery and differential delay on the magnetic coupling signals by an interlocking circuit for reducing time difference and signal loss of the magnetic coupling signals; and when the interlocking circuit determines that the magnetic coupling signals have substantially no time difference and no signal loss, transforming the magnetic coupling signals into a first driving signal and a second driving signal by a switch circuit, a driver circuit and an output pad group to drive a backend driving loop.

High power multiple frequency coupling generator and driving method thereof

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.

Semiconductor devices including gate structures with gate spacers

Semiconductor devices and methods of manufacturing thereof

An ear tag module includes a rod member, a spike, a circuit component, and a temperature sensor. The spike is disposed on one side of the rod member, and the circuit component is disposed on another side of the rod member. The temperature sensor is electrically connected to the circuit component. When the spike penetrates an ear, the ear is in contact with a sensing area of the rod member, and the temperature sensor is located in the rod member to detect a temperature of the ear and transmit at least one temperature sensing information to the circuit component.

Ear tag module

A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

Semiconductor device and manufacturing method thereof

An intelligent diagnosis system for a power module. The system includes a power module, a hardware checking module and a diagnostic module. The power module has a temperature sensing element for obtaining a temperature difference between a starting minimum temperature and a current temperature. The hardware checking module has a current sensing element, a voltage sensing element and a magnetic coupling closed loop detection element for obtaining the current, the output voltage and the input voltage of the power module, and the hardware loop status, respectively. The diagnostic module calculates the number of cycles that have been operated, a measured impedance and an instantaneous power based on those measurement results, and calculating a risk index based on the number of cycles that have been operated, the temperature difference, the measured impedance, the instantaneous power and the hardware loop status, thereby determining the accumulation of the abnormality index record.

Intelligent diagnosis system for power module and method thereof

Growing community of inventors

Miaoli County, Taiwan

Chih-Chung Chiu