United Microelectronics Corp.

Chih-Chung Chen

Yu-Ren Wang

Tsuo-Wen Lu

Chien-Liang Lin

Po-Chang Lin

Yi-Wei Chen

Chun-Hsien Lin

Shih-Hung Tsai

Ying-Wei Yen

Shao-Wei Wang

Po-Kuang Hsieh

Man-Ling Lu

Jhen-Cyuan Li

Wen-Yi Teng

Sheng-Hsu Liu

Keng-Jen Lin

Chung-Min Tsai

Bo-Han Huang

Tsung-Chieh Yang

Chin-Cheng Chien

An-Chi Liu

Shih-Chieh Hsu

Shu-Yen Chan

Wei-Jen Chen

Tsai-Yu Wen

Shin-Chi Chen

Chia-Lung Chang

Jei-Ming Chen

Chih-Yueh Li

Chi-Horn Pai

Shao-Hua Hsu

Chun-Chia Chen

Yi-Ching Wu

Chun-Wei Hsu

Zen-Jay Tsai

Huang-Ren Wei

Ying-Hung Chou

Yu-Min Lin

Shih-Hao Su

Pei-Ching Yeh

Wei-Lun Chou

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50&#xb0; C. to 100&#xb0; C., and a duration of the baking process is between 5 seconds to 120 seconds.

Rinse process after forming fin-shaped structure

A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120&#x2dc;190 degrees Celsius. The substrate is subjected to a cleaning process.

Method of forming a semiconductor device

A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

Insulating layer next to fin structure and method of removing fin structure

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10&#xb0; to about 55&#xb0;. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Bottom-up epitaxy growth on air-gap buffer

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.

Method for fabricating shallow trench isolation structure

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Method for manufacturing shallow trench isolation

A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Method for processing high-k dielectric layer

A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

Method for fabricating semiconductor device and PMOS device fabricated by the method

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Manufacturing method for metal gate using ion implantation

Growing community of inventors

Tainan, Taiwan

Chih-Chung Chen