Mediatek Corporation

Industrial Technology Research Institute

National Sun Yat-sen University of Kaohsiung

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Chun Hsu

Sheng-Mou Lin

Ken-Huang Lin

Chun-Yih Wu

Hung-Hsuan Lin

Hsin-Lung Su

Ming-Da Tsai

Wen-Chou Wu

Ching-Juinn Huang

Yuan-Yu Fu

Jui-Chih Kao

Chuan-Fang Su

Hsing-Wang Chen

Rung-Shiang Chen

A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

Semiconductor package integrated with memory die

A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.

Semiconductor package with three-dimensional antenna

An integrated circuit apparatus includes a substrate, an IC chip disposed above the substrate, and an electromagnetic shielding layer disposed on a surface of the substrate. The IC chip includes an electromagnetic coupling device. The electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate.

Integrated circuit apparatus

A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.

A radiation pattern insulator and an antennae system thereof are proposed. The radiation pattern insulator includes a dielectric substrate and a plurality of radiation pattern insulation elements. The dielectric substrate allocated between a plurality of antennae includes a top surface and a bottom surface, and a normal direction of the dielectric substrate is substantially perpendicular to propagation directions of electromagnetic waves radiated from the antennae. In addition, the radiation pattern insulation elements are allocated on the top surface or the bottom surface of the dielectric substrate, or alternatively, all allocated on the top surface and the bottom surface.

Radiation pattern insulator and multiple antennae system thereof and communication device using the multiple antennae system

Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.

Growing community of inventors

Taipei, Taiwan

Chih-Chun Hsu