Vanguard International Semiconductor Corporation

Chih-Chuan Ke

Yung-Chang Chen

Po-Yuan Tang

Jian-Yuan Hsiao

Yin-Ting Lin

Yi-Ling Hung

A sensing amplifier circuit includes first and second P-type transistors and first and second N-type transistors. The first P-type transistor includes a gate coupled to an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node. The second P-type transistor includes a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor includes a gate coupled to the input node, a drain coupled to the output node, and a source coupled to ground. The second N-type transistor includes a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor includes an N-type well region that is electrically connected to the source and bulk of the first P-type transistor.

Sensing amplifier circuit and memory device

A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a bit voltage and a second terminal coupled to a first node. The diode has an anode coupled to the first node and a cathode coupled to a second node. The second node receives a word voltage. The first transistor has a control electrode, a first electrode coupled to the first node, and a second electrode.

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Taipei, Taiwan

Chih-Chuan Ke