Raydium Semiconductor Corporation

Chih-Chuan Huang

Ko-Yang Tso

Wen-Tsung Lin

Hui-Wen Miao

Sung-Bo Chen

Chien-Hao Chen

Yu-Lung Lo

Chien-Ming Chen

Yu-Chun Lin

Shang-Han Yu

Shun-Yuan Wang

Chih-Hsien Jen

Chih-Hao Wu

Ching Chuan Chiu

Hsin-Yeh Wu

A source driver includes a phase generator, a control circuit, and an output circuit. The phase generator is configured to generate a plurality of output clock signals according to an input clock signal, in which the phases of the output clock signals are different from each other. The control circuit is configured to sequentially generate a plurality of control signals according to the output clock signals and a latch signal. The output circuit is configured to sequentially output a plurality of data voltages separately according to the control signals.

Source driver

A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area&#x2dc;a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.

Display apparatus and inter-chip bus thereof

A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.

Power saving control apparatus and power saving control method applied to display driving circuit

The present invention provides a display panel driving circuit and compensation method thereof. The display panel driving circuit comprises a near end load, a far end load, an operating circuit and a pre-charging control circuit. The operating circuit is configured to receive display data. The pre-charging control circuit is coupled to the near end load and the far end load respectively. The pre-charging control circuit outputs a first signal and a second signal to the near end load and the far end load respectively according to the display data that a first waveform from the near end load is the same as a second waveform from the far end load.

Display panel driving circuit and compensation method thereof

A random chopper control circuit is disclosed. The random chopper control circuit is coupled to an operational amplifier. The random chopper control circuit includes a random generator. The random generator is configured to generate a random chopper control signal and output the random chopper control signal to the operational amplifier to control an operation of the operational amplifier.

Random chopper control circuit

A driving circuit includes at least one reference voltage source, at least one offset unit, and at least one buffer module. The at least one reference voltage source generates a reference voltage. The at least one offset unit generates an offset voltage, wherein the offset voltage and the reference voltage form a judging voltage range. The at least one buffer module has a first input end, a second input end, and an output end, wherein the first input end receives an analog voltage; the at least one reference voltage source is connected with the second input end; the at least one buffer module, according as whether the analog voltage is within the judging voltage range, outputs a pass logic signal or a fail logic signal at the output end. Particularly, the buffer module has Built-In-Self-Test (BIST) function and can increase test efficiency and voltage accuracy.

Driving circuit having built-in-self-test function

A driving circuit for connecting a display module is provided. The driving circuit includes a polarity control module, an output control module, and a detecting module. The polarity control module provides a polarity control signal. The output control module is connected with the polarity control module and provides a plurality of output control signals. The detecting module is coupled with the polarity control module and the output control module, wherein the detecting module detects the polarity control signal and selectively controls the output control module to operate in at least one of a first control mode and a second control mode to control the output control signals.

Driving circuit

The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

Controlling apparatus and controlling method for signal outputing circuit and video system

A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.

Growing community of inventors

Zhubei, Taiwan

Chih-Chuan Huang