Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Chien Hung

Chao-Hsin Chang

Chia-Hsiang Chen

Hsien-Wen Chang

Kuang-Hui Chang

Ming-Fa Chen

Tsu Shih

Po-Tao Chu

Yuan-Chang Huang

Tzu-Yu Lin

Li-Kong Turn

Hung-Chih Chen

Ching-Wen Cho

Chia-Hung Lai

Mingchu King

Han-Ming Sheng

Fu-Tien Wong

Renn-Shyan Yeh

Der-Fang Huang

Hsiang-Chung Liu

Ming-Huei Tseng

Shih-Shiung Cheu

De-Ming Liang

Chun-Mei Lee

Yao-Chanet Chu

A method of forming circuit patterns on a semiconductor wafer using two different image steppers having nonaligned optical image systems achieves optical alignment of multiple overlays with high accuracy. A first alignment mark is imaged by the first stepper onto a material layer deposited on the wafer, and a second alignment mark is imaged onto a subsequently deposited material layer using the second stepper. Alignment of the two marks, and thus of successively imaged, overlying circuit patterns, is achieved by translating the optical coordinates of the second alignment system into the those of the first alignment system, and then making corresponding two dimensional adjustment of the wafer position relative to the second stepper.

Method of forming circuit patterns on semiconductor wafers using two optical steppers having nonaligned imaging systems

A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.

Frame layout to monitor overlay performance of chip composed of multi-exposure images

A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

Test pattern for monitoring metal corrosion on integrated circuit wafers

A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

Method for determining a cause for defects in a film deposited on a wafer

An apparatus and method for determining local de-focus problems on a real time basis in a wafer exposure system. The distance of a wafer from an objective lens and rotation of the wafer about two orthogonal axis at each field position is adjusted to achieve optimum focus for each field of the wafer. The rotational data is fed to a computer and analyzed to determine if any of the rotational angles or if the difference between individual rotational angle and the mean rotational angle exceed critical angles. If any of the critical angles are exceeded local de-focus will occur and the exposure system must be checked for defects. If none of the critical angles are exceeded processing continues with the next wafer. The comparison of the rotational angles to the critical angles is performed for each wafer before continuing with the next wafer so that problems are discovered on a real time basis.

Real time local defocus monitor system using maximum and mean angles of

The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.

Method of stripping photoresist from Al bonding pads that prevents

A low cost, fast method for evaluating the effects of lens heating in a step and repeat projection system is disclosed. The first step is to form a series of photoresist images on a single substrate in the same way as would be done during normal stepping and repeating. The first few images, located centrally, will be produced by a cool lens. As more images are generated, the lens gradually heats up so that the final few images, which are placed alongside the `cool` images, will be produced by a hot lens. Critical dimension bars are present in all image fields (at diagonally opposite corners and in the center), their size in the developed photoresist being an indication of the extent to which the focal plane has drifted. This is then used to compute correction factors for the manufacturer's scaling constants and/or to evaluate the extent, if any, of curvature of field in the projected images.

Method to monitor lens heating effects

Method for monitoring metal corrosion on integrated circuit wafers

This invention provides a method for removing metal etch residue of silicon nodules, resulting from a small percentage of silicon in the metal, without causing overetch damage to the photoresist pattern, the metal electrode pattern, or to dielectric layers. The metal conductor layer is partially etched leaving from 20 to 80 percent of the original thickness. Any residue of silicon nodules formed during this partial etching is then removed using ion bombardment. The remainder of the metal conductor layer is then etched. A short overetch period is used to remove any remaining residue of silicon nodules. The overetch period is short and there is no deterioration of the photoresist or exposed edges of the electrode pattern.

Method to remove residue of metal etch

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Hsin-Chu, Taiwan

Chih-Chien Hung