Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Chien Chi

Hung-Wen Su

Szu-Ping Tung

Ching-Hua Hsieh

Pei-Hsuan Lee

Huang-Yi Huang

Shu-Cheng Chin

Yao-Jen Chang

Chen-Yuan Kao

Po-Cheng Shih

Kai-Shiang Kuo

Jun-Yi Ruan

Chi-Feng Lin

Chung-Chi Ko

Yao-Min Liu

Tze-Liang Lee

Chia-Cheng Chou

Hsiao-Kuan Wei

Hsin-Yun Hsu

Jui-Fen Chien

Ya-Lien Lee

Mei-Ling Chen

Kuan-Chia Chen

Hsin-Ying Peng

Po-Hsiang Huang

Ming-Hsing Tsai

Shing-Chyang Pan

Hui Yu Lee

Wen-Sheh Huang

Chih-Hsiang Chang

Su-Jen Sung

Szu-Hua Wu

Jung-Tang Wu

Jen Hung Wang

Yen-Chun Lin

Chia-Pang Kuo

Chih-Yi Chang

Jen-Chun Wang

Ming-Yuan Gao

Chen-Yi Niu

Pao-Sheng Chen

Keng-Chu Lin

Sung-Li Wang

Shuen-Shin Liang

Chia-Hung Chu

Cheng-Wei Chang

Hsu-Kai Chang

Yi-Ying Liu

Chien-Shun Liao

Cheng-Hui Weng

Yu-Ying Liu

Wei Hsiang Chan

Kai-Ting Huang

Jau-Jiun Huang

Barrier-free interconnects and methods of fabrication thereof are disclosed herein. An exemplary interconnect structure has a conductive line disposed over a conductive via. The conductive line has a first conductive plug disposed in a first dielectric layer, and the first conductive plug includes an electrically conductive non-metal material, such as graphite. The conductive via includes a second conductive plug disposed in a second dielectric layer, and the second conductive plug includes a metal material, such as tungsten, ruthenium, molybdenum, or combinations thereof. The first conductive plug physically contacts the second conductive plug and the second dielectric layer. The second conductive plug physically contacts the second dielectric layer. Spacers (which are insulators) may be disposed between sidewalls of the first conductive plug and the first dielectric layer. The spacers may further be disposed between the first dielectric layer and the second dielectric layer.

Graphite-based interconnects and methods of fabrication thereof

Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

Semiconductor devices and methods of formation

A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

Interconnect structure including graphite and method forming same

A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.

Interconnect structure of semiconductor device

A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.

Conductive structures with barriers and liners of varying thicknesses

A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.

Graphene liners and caps for semiconductor structures

A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Semiconductor device having a contact structure

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Method of forming interconnect structure having a barrier layer

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Multi-layer film device and method

A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

Method of forming an interconnect structure having an air gap and structure thereof

Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnect

A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

Method of making a contact structure

The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Hybrid conductive structures

A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.

Semiconductor device, method and machine of manufacture

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Selective capping processes and structures formed thereby

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Hsinchu, Taiwan

Chih-Chien Chi