Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Chih Chieh Yeh

Tsung-Lin Lee

Yee-Chia Yeo

Hung-Li Chiang

Wen Jer Tsai

Cheng-Yi Peng

Feng Yuan

Cheng-Hsien Wu

I-Sheng Chen

Yu-Lin Yang

Tzu-Chiang Chen

Chih-Sheng Chang

Tung Ying Lee

Yi Ying Liao

Tao Cheng Lu

Wei-Jen Lai

Chao-Ching Cheng

Chia-Cheng Ho

Ming-Shuan Li

Chi-Wen Liu

Hung-Ming Chen

Zi-Ang Su

Clement Hsingjen Wann

Meng-Hsuan Hsiao

Chih Yuan Lu

Chang-Yun Chang

Jung-Piao Chiu

Szu-Wei Huang

Wen-Hsing Hsieh

Chih-Hung Wang

Jon-Hsu Ho

Tsu-Hsiu Perng

Chen-Feng Hsu

Yen-Ming Chen

Chih-Hsin Ko

Chih-Hao Chang

Liang-Yin Chen

Chan-Lon Yang

Shao-Ming Yu

Chung-Cheng Wu

Xiong-Fei Yu

Jeff J Xu

Wei-Sheng Yun

Chien-Hsun Wang

Chih-Hsiang Chang

Li-Shyue Lai

Huan-Sheng Wei

Han Chao Lai

Chia-Ju Chou

Shih-Hao Lin

Yuan-Hung Chiu

Jeng-Ya David Yeh

Tahui Wang

Zhiqiang Wu

Tao-Cheng Lu

Tsz-Mei Kwok

Da-Wen Lin

Ken-Ichi Goto

Yi-Ming Sheu

Tsung-Hsing Yu

Chien-Chih Lin

Ming-Lung Cheng

Chih-Ching Wang

Yin Jen Chen

Ching-Fang Huang

Tsai-Yu Huang

Szu-Chi Yang

Tsung-Hung Lee

Tzung Ting Han

Choh Fei Yeap

Po-Kai Hsiao

Shaw Hung Ku

Chien-Chih Lee

Shao Hong Ku

Huang-Hsuan Lin

Ming Shiang Chin

Wen Her Tsai

Yi Yang Liao

Hung Yueh Chen

Cheng-Ting Ding

Allen Chien

Chun Lein Su

Shu-Hua Wu

A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Multi-gate device and method of fabrication thereof

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.

Multi-gate devices and method of forming the same

A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region.

Gate stacks for stack-fin channel I/O devices and nanowire channel core devices

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

Semiconductor device and method

Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Device and method of fabricating multigate devices having different channel configurations

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Semiconductor device and manufacturing method thereof

A semiconductor structure includes N-type MBC transistors formed over a first region of a hybrid substrate and P-type MBC transistors formed over a second region of the hybrid substrate. The first region and the second region have top surfaces with different crystal orientations. Particularly, the first region for forming the N-type MBC transistors includes a top surface having a () crystal plane and the second region for forming P-type MBC transistors includes a top surface having a () crystal plane.

Semiconductor structures with a hybrid substrate

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.

Forming ESD devices using multi-gate compatible processes

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Semiconductor devices and methods of fabricating the same

The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.

Complementary bipolar junction transistor

The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

Forming ESD devices using multi-gate compatible processess

A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.

Method and structure for diodes with backside contacts

The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

Bipolar junction device

Growing community of inventors

Taipei, Taiwan

Chih Chieh Yeh