United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Chih-Chieh Tsai

Yi-Wei Chen

Tsun-Min Cheng

Pin-Hong Chen

Tzu-Chieh Chen

Kai-Jiun Chang

Yi-An Huang

Chia-Chen Wu

Chi-Mao Hsu

Chih-Chien Liu

Chun-Chieh Chiu

Hsin-Fu Huang

Shih-Fang Tzou

Tzu-Hao Liu

Wei-Hsin Liu

Ji-Min Lin

Li-Wei Feng

Ying-Chiao Wang

Chia-Lung Chang

Jui-Min Lee

Chung-Yen Feng

Po-Chih Wu

A monitor wafer is provided. The monitor wafer includes a substrate and a cleaning layer. The cleaning layer is disposed on a bottom surface of the substrate. The cleaning layer is configured to remove particles from the substrate and/or a processing tool.

Monitor wafer and method of using the same

A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

Buried word line of a dynamic random access memory and method for fabricating the same

The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Storage node contact structure of a memory device

A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Semiconductor device and method for fabricating the same

A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

Bit line utilized in DRAM

A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same

A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

Method of forming a semiconductor structure

Storage node contact structure of a memory device and manufacturing methods thereof

A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50&#xb0; C. and 100&#xb0; C., and the temperature of the chamber is between 300&#xb0; C. and 350&#xb0; C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300&#xb0; C. and 350&#xb0; C., and the duration of the annealing process is between 50 seconds and 60 seconds.

Fabricating method of cobalt silicide layer coupled to contact plug

A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.

Growing community of inventors

Kaohsiung, Taiwan

Chih-Chieh Tsai